mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7b837d8c75
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
50 lines
2.0 KiB
LLVM
50 lines
2.0 KiB
LLVM
; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
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define <2 x float> @cvtf32fxpu(<2 x i32> %a) nounwind readnone ssp {
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; CHECK-LABEL: cvtf32fxpu:
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; CHECK: ucvtf.2s v0, v0, #9
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; CHECK: ret
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%vcvt_n1 = tail call <2 x float> @llvm.arm64.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> %a, i32 9)
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ret <2 x float> %vcvt_n1
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}
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define <2 x float> @cvtf32fxps(<2 x i32> %a) nounwind readnone ssp {
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; CHECK-LABEL: cvtf32fxps:
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; CHECK: scvtf.2s v0, v0, #12
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; CHECK: ret
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%vcvt_n1 = tail call <2 x float> @llvm.arm64.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32> %a, i32 12)
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ret <2 x float> %vcvt_n1
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}
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define <4 x float> @cvtqf32fxpu(<4 x i32> %a) nounwind readnone ssp {
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; CHECK-LABEL: cvtqf32fxpu:
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; CHECK: ucvtf.4s v0, v0, #18
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; CHECK: ret
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%vcvt_n1 = tail call <4 x float> @llvm.arm64.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> %a, i32 18)
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ret <4 x float> %vcvt_n1
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}
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define <4 x float> @cvtqf32fxps(<4 x i32> %a) nounwind readnone ssp {
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; CHECK-LABEL: cvtqf32fxps:
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; CHECK: scvtf.4s v0, v0, #30
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; CHECK: ret
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%vcvt_n1 = tail call <4 x float> @llvm.arm64.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> %a, i32 30)
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ret <4 x float> %vcvt_n1
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}
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define <2 x double> @f1(<2 x i64> %a) nounwind readnone ssp {
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%vcvt_n1 = tail call <2 x double> @llvm.arm64.neon.vcvtfxu2fp.v2f64.v2i64(<2 x i64> %a, i32 12)
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ret <2 x double> %vcvt_n1
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}
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define <2 x double> @f2(<2 x i64> %a) nounwind readnone ssp {
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%vcvt_n1 = tail call <2 x double> @llvm.arm64.neon.vcvtfxs2fp.v2f64.v2i64(<2 x i64> %a, i32 9)
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ret <2 x double> %vcvt_n1
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}
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declare <4 x float> @llvm.arm64.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
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declare <4 x float> @llvm.arm64.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
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declare <2 x float> @llvm.arm64.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
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declare <2 x float> @llvm.arm64.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
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declare <2 x double> @llvm.arm64.neon.vcvtfxu2fp.v2f64.v2i64(<2 x i64>, i32) nounwind readnone
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declare <2 x double> @llvm.arm64.neon.vcvtfxs2fp.v2f64.v2i64(<2 x i64>, i32) nounwind readnone
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