mirror of
https://github.com/c64scene-ar/llvm-6502.git
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e626ee51b6
I noticed some odd looking cases where addr64 wasn't set when storing to a pointer in an SGPR. This seems to be intentional, and partially tested already. The documentation seems to describe addr64 in terms of which registers addressing modifiers come from, but I would expect to always need addr64 when using 64-bit pointers. If no offset is applied, it makes sense to not need to worry about doing a 64-bit add for the final address. A small immediate offset can be applied, so is it OK to not have addr64 set if a carry is necessary when adding the base pointer in the resource to the offset? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217785 91177308-0d34-0410-b5e6-96231b3b80d8
133 lines
5.0 KiB
LLVM
133 lines
5.0 KiB
LLVM
; RUN: llc -march=r600 -mcpu=SI -show-mc-encoding -verify-machineinstrs < %s | FileCheck %s
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declare i32 @llvm.r600.read.tidig.x() readnone
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;;;==========================================================================;;;
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;;; MUBUF LOAD TESTS
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;;;==========================================================================;;;
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; MUBUF load with an immediate byte offset that fits into 12-bits
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; CHECK-LABEL: @mubuf_load0
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; CHECK: BUFFER_LOAD_DWORD v{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0 offset:0x4 ; encoding: [0x04,0x00,0x30,0xe0
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define void @mubuf_load0(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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entry:
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%0 = getelementptr i32 addrspace(1)* %in, i64 1
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%1 = load i32 addrspace(1)* %0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; MUBUF load with the largest possible immediate offset
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; CHECK-LABEL: @mubuf_load1
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; CHECK: BUFFER_LOAD_UBYTE v{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0 offset:0xfff ; encoding: [0xff,0x0f,0x20,0xe0
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define void @mubuf_load1(i8 addrspace(1)* %out, i8 addrspace(1)* %in) {
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entry:
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%0 = getelementptr i8 addrspace(1)* %in, i64 4095
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%1 = load i8 addrspace(1)* %0
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store i8 %1, i8 addrspace(1)* %out
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ret void
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}
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; MUBUF load with an immediate byte offset that doesn't fit into 12-bits
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; CHECK-LABEL: @mubuf_load2
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; CHECK: BUFFER_LOAD_DWORD v{{[0-9]}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 ; encoding: [0x00,0x80,0x30,0xe0
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define void @mubuf_load2(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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entry:
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%0 = getelementptr i32 addrspace(1)* %in, i64 1024
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%1 = load i32 addrspace(1)* %0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; MUBUF load with a 12-bit immediate offset and a register offset
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; CHECK-LABEL: @mubuf_load3
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; CHECK-NOT: ADD
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; CHECK: BUFFER_LOAD_DWORD v{{[0-9]}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:0x4 ; encoding: [0x04,0x80,0x30,0xe0
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define void @mubuf_load3(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i64 %offset) {
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entry:
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%0 = getelementptr i32 addrspace(1)* %in, i64 %offset
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%1 = getelementptr i32 addrspace(1)* %0, i64 1
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%2 = load i32 addrspace(1)* %1
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store i32 %2, i32 addrspace(1)* %out
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ret void
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}
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;;;==========================================================================;;;
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;;; MUBUF STORE TESTS
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;;;==========================================================================;;;
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; MUBUF store with an immediate byte offset that fits into 12-bits
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; CHECK-LABEL: @mubuf_store0
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; CHECK: BUFFER_STORE_DWORD v{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0 offset:0x4 ; encoding: [0x04,0x00,0x70,0xe0
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define void @mubuf_store0(i32 addrspace(1)* %out) {
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entry:
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%0 = getelementptr i32 addrspace(1)* %out, i64 1
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store i32 0, i32 addrspace(1)* %0
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ret void
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}
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; MUBUF store with the largest possible immediate offset
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; CHECK-LABEL: @mubuf_store1
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; CHECK: BUFFER_STORE_BYTE v{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0 offset:0xfff ; encoding: [0xff,0x0f,0x60,0xe0
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define void @mubuf_store1(i8 addrspace(1)* %out) {
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entry:
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%0 = getelementptr i8 addrspace(1)* %out, i64 4095
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store i8 0, i8 addrspace(1)* %0
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ret void
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}
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; MUBUF store with an immediate byte offset that doesn't fit into 12-bits
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; CHECK-LABEL: @mubuf_store2
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; CHECK: BUFFER_STORE_DWORD v{{[0-9]}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0 addr64 ; encoding: [0x00,0x80,0x70,0xe0
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define void @mubuf_store2(i32 addrspace(1)* %out) {
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entry:
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%0 = getelementptr i32 addrspace(1)* %out, i64 1024
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store i32 0, i32 addrspace(1)* %0
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ret void
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}
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; MUBUF store with a 12-bit immediate offset and a register offset
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; CHECK-LABEL: @mubuf_store3
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; CHECK-NOT: ADD
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; CHECK: BUFFER_STORE_DWORD v{{[0-9]}}, v[{{[0-9]:[0-9]}}], s[{{[0-9]:[0-9]}}], 0 addr64 offset:0x4 ; encoding: [0x04,0x80,0x70,0xe0
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define void @mubuf_store3(i32 addrspace(1)* %out, i64 %offset) {
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entry:
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%0 = getelementptr i32 addrspace(1)* %out, i64 %offset
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%1 = getelementptr i32 addrspace(1)* %0, i64 1
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store i32 0, i32 addrspace(1)* %1
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ret void
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}
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; CHECK-LABEL: @store_sgpr_ptr
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; CHECK: BUFFER_STORE_DWORD v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0
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define void @store_sgpr_ptr(i32 addrspace(1)* %out) #0 {
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store i32 99, i32 addrspace(1)* %out, align 4
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ret void
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}
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; CHECK-LABEL: @store_sgpr_ptr_offset
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; CHECK: BUFFER_STORE_DWORD v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:0x28
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define void @store_sgpr_ptr_offset(i32 addrspace(1)* %out) #0 {
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%out.gep = getelementptr i32 addrspace(1)* %out, i32 10
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store i32 99, i32 addrspace(1)* %out.gep, align 4
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ret void
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}
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; CHECK-LABEL: @store_sgpr_ptr_large_offset
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; CHECK: BUFFER_STORE_DWORD v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64
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define void @store_sgpr_ptr_large_offset(i32 addrspace(1)* %out) #0 {
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%out.gep = getelementptr i32 addrspace(1)* %out, i32 32768
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store i32 99, i32 addrspace(1)* %out.gep, align 4
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ret void
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}
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; CHECK-LABEL: @store_vgpr_ptr
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; CHECK: BUFFER_STORE_DWORD v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64
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define void @store_vgpr_ptr(i32 addrspace(1)* %out) #0 {
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%tid = call i32 @llvm.r600.read.tidig.x() readnone
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%out.gep = getelementptr i32 addrspace(1)* %out, i32 %tid
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store i32 99, i32 addrspace(1)* %out.gep, align 4
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ret void
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}
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