Chad Rosier 67c325e9f0 [AArch64] Lower sdiv x, pow2 using add + select + shift. ... The target-independent DAGcombiner will generate: asr w1, X, #31 w1 = splat sign bit. add X, X, w1, lsr #28 X = X + 0 or pow2-1 asr w0, X, asr #4 w0 = X/pow2 However, the add + shifts is expensive, so generate: add w0, X, 15 w0 = X + pow2-1 cmp X, wzr X - 0 csel X, w0, X, lt X = (X < 0) ? X + pow2-1 : X; asr w0, X, asr 4 w0 = X/pow2 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213758 91177308-0d34-0410-b5e6-96231b3b80d8		2014-07-23 14:57:52 +00:00
..
ADT	AArch64: remove arm64 triple enumerator.	2014-07-23 12:32:47 +00:00
Analysis	Match semantics of PointerMayBeCapturedBefore to its name by default	2014-07-21 21:30:22 +00:00
AsmParser
Bitcode	Add a dereferenceable attribute	2014-07-18 15:51:28 +00:00
CodeGen	[SDAG] Refactor the code for inserting a newly allocated SDNode into the	2014-07-22 04:07:55 +00:00
Config	Drop the udis86 wrapper from llvm::sys	2014-07-17 20:05:29 +00:00
DebugInfo
ExecutionEngine	[MCJIT] Refactor and add stub inspection to the RuntimeDyldChecker framework.	2014-07-22 22:47:39 +00:00
IR	AVX-512: Fixed intrinsic of VSQRTPS/PD instructions.	2014-07-22 11:07:31 +00:00
IRReader
LineEditor
Linker
LTO
MC	[MC] Pass MCSymbolData to needsRelocateWithSymbol	2014-07-20 23:15:06 +00:00
Object	Correct the ownership passing semantics of object::createBinary and make them explicit in the type system.	2014-07-21 16:26:24 +00:00
Option
ProfileData
Support	[PowerPC] ELFv2 MC support for .localentry directive	2014-07-20 23:06:03 +00:00
TableGen
Target	[AArch64] Lower sdiv x, pow2 using add + select + shift.	2014-07-23 14:57:52 +00:00
Transforms	MergedLoadStoreMotion pass	2014-07-18 19:13:09 +00:00
CMakeLists.txt
InitializePasses.h	Templatify RegionInfo so it works on MachineBasicBlocks	2014-07-19 18:29:29 +00:00
LinkAllIR.h
LinkAllPasses.h	MergedLoadStoreMotion pass	2014-07-18 19:13:09 +00:00
module.modulemap
module.modulemap.build
Pass.h
PassAnalysisSupport.h
PassInfo.h
PassManager.h
PassRegistry.h
PassSupport.h