Chad Rosier 67c325e9f0 [AArch64] Lower sdiv x, pow2 using add + select + shift. ... The target-independent DAGcombiner will generate: asr w1, X, #31 w1 = splat sign bit. add X, X, w1, lsr #28 X = X + 0 or pow2-1 asr w0, X, asr #4 w0 = X/pow2 However, the add + shifts is expensive, so generate: add w0, X, 15 w0 = X + pow2-1 cmp X, wzr X - 0 csel X, w0, X, lt X = (X < 0) ? X + pow2-1 : X; asr w0, X, asr 4 w0 = X/pow2 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213758 91177308-0d34-0410-b5e6-96231b3b80d8		2014-07-23 14:57:52 +00:00
..
CostTable.h	Add a overload to CostTable which allows it to infer the size of the table.	2013-08-09 19:33:32 +00:00
Target.td	Condition codes AL and NV are invalid in the aliases that use	2014-06-10 13:11:35 +00:00
TargetCallingConv.h	ARM: HFAs must be passed in consecutive registers	2014-05-09 14:01:47 +00:00
TargetCallingConv.td	ARM: HFAs must be passed in consecutive registers	2014-05-09 14:01:47 +00:00
TargetFrameLowering.h	Re-apply r211399, "Generate native unwind info on Win64" with a fix to ignore SEH pseudo ops in X86 JIT emitter.	2014-06-25 12:41:52 +00:00
TargetInstrInfo.h	The hazard recognizer only needs a subtarget, not a target machine	2014-06-13 22:38:52 +00:00
TargetIntrinsicInfo.h	Trailing whitespace.	2014-07-23 00:42:52 +00:00
TargetItinerary.td
TargetJITInfo.h	Trailing whitespace.	2014-07-23 00:42:52 +00:00
TargetLibraryInfo.h	Trailing whitespace.	2014-07-23 00:42:52 +00:00
TargetLowering.h	[AArch64] Lower sdiv x, pow2 using add + select + shift.	2014-07-23 14:57:52 +00:00
TargetLoweringObjectFile.h	CodeGen: Stick constant pool entries in COMDAT sections for WinCOFF	2014-07-14 22:57:27 +00:00
TargetMachine.h	Move the verbose asm option to be part of the options struct and	2014-05-20 23:59:50 +00:00
TargetOpcodes.h	Replace PROLOG_LABEL with a new CFI_INSTRUCTION.	2014-03-07 06:08:31 +00:00
TargetOptions.h	Add a new attribute called 'jumptable' that creates jump-instruction tables for functions marked with this attribute.	2014-06-05 19:29:43 +00:00
TargetRegisterInfo.h	[RegisterCoalescer] Moving the RegisterCoalescer subtarget hook onto the TargetRegisterInfo instead of the TargetSubtargetInfo.	2014-07-16 20:13:31 +00:00
TargetSchedule.td	Move Post RA Scheduling flag bit into SchedMachineModel	2014-07-15 22:39:58 +00:00
TargetSelectionDAG.td	Fix typos	2014-07-17 17:50:22 +00:00
TargetSelectionDAGInfo.h	Trailing whitespace.	2014-07-23 00:42:52 +00:00
TargetSubtargetInfo.h	Trailing whitespace.	2014-07-23 00:42:52 +00:00