Chad Rosier 67c325e9f0 [AArch64] Lower sdiv x, pow2 using add + select + shift. ... The target-independent DAGcombiner will generate: asr w1, X, #31 w1 = splat sign bit. add X, X, w1, lsr #28 X = X + 0 or pow2-1 asr w0, X, asr #4 w0 = X/pow2 However, the add + shifts is expensive, so generate: add w0, X, 15 w0 = X + pow2-1 cmp X, wzr X - 0 csel X, w0, X, lt X = (X < 0) ? X + pow2-1 : X; asr w0, X, asr 4 w0 = X/pow2 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213758 91177308-0d34-0410-b5e6-96231b3b80d8		2014-07-23 14:57:52 +00:00
..
Analysis	Make use of the align parameter attribute for all pointer arguments	2014-07-22 16:58:55 +00:00
AsmParser	Add a dereferenceable attribute	2014-07-18 15:51:28 +00:00
Bitcode	Add a dereferenceable attribute	2014-07-18 15:51:28 +00:00
CodeGen	[AArch64] Lower sdiv x, pow2 using add + select + shift.	2014-07-23 14:57:52 +00:00
DebugInfo
ExecutionEngine	AArch64: remove arm64 triple enumerator.	2014-07-23 12:32:47 +00:00
IR	Rename metadata llvm.loop.vectorize.unroll to llvm.loop.vectorize.interleave.	2014-07-21 23:11:03 +00:00
IRReader
LineEditor
Linker
LTO	AArch64: remove arm64 triple enumerator.	2014-07-23 12:32:47 +00:00
MC	AArch64: remove arm64 triple enumerator.	2014-07-23 12:32:47 +00:00
Object	AArch64: remove arm64 triple enumerator.	2014-07-23 12:32:47 +00:00
Option
ProfileData
Support	AArch64: remove "arm64_be" support in favour of "aarch64_be".	2014-07-23 12:58:11 +00:00
TableGen	[TableGen] Allow shift operators to take bits<n>	2014-07-17 17:04:27 +00:00
Target	[AArch64] Lower sdiv x, pow2 using add + select + shift.	2014-07-23 14:57:52 +00:00
Transforms	We may visit a call that uses an alloca multiple times in callUsesLocalStack, sometimes with IsNocapture true and sometimes with IsNocapture false. We accidentally skipped work we needed to do in the IsNocapture=false case if we were called with IsNocapture=true the first time. Fixes PR20405!	2014-07-23 06:24:49 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile