Juergen Ributzka 06bb1ca1e0 Reapply [FastISel][AArch64] Add support for more addressing modes (r215597). ... Note: This was originally reverted to track down a buildbot error. Reapply without any modifications. Original commit message: FastISel didn't take much advantage of the different addressing modes available to it on AArch64. This commit allows the ComputeAddress method to recognize more addressing modes that allows shifts and sign-/zero-extensions to be folded into the memory operation itself. For Example: lsl x1, x1, #3 --> ldr x0, [x0, x1, lsl #3] ldr x0, [x0, x1] sxtw x1, w1 lsl x1, x1, #3 --> ldr x0, [x0, x1, sxtw #3] ldr x0, [x0, x1] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216013 91177308-0d34-0410-b5e6-96231b3b80d8		2014-08-19 19:44:17 +00:00
..
AArch64	Reapply [FastISel][AArch64] Add support for more addressing modes (r215597).	2014-08-19 19:44:17 +00:00
ARM	Reapply [FastISel] Let the target decide first if it wants to materialize a constant (215588).	2014-08-19 19:05:24 +00:00
CPP
Generic
Hexagon
Inputs
Mips	Fix fmul combines with constant splat vectors	2014-08-16 10:14:19 +00:00
MSP430
NVPTX
PowerPC	Reapply [FastISel] Let the target decide first if it wants to materialize a constant (215588).	2014-08-19 19:05:24 +00:00
R600	R600/SI: Move all fabs / fneg handling to patterns	2014-08-15 18:42:22 +00:00
SPARC
SystemZ
Thumb	ARM: Fix and re-enable load/store optimizer for Thumb1.	2014-08-15 17:00:30 +00:00
Thumb2	ARM: do not generate BLX instructions on Cortex-M CPUs.	2014-08-06 11:13:14 +00:00
X86	Reapply [FastISel][X86] Add large code model support for materializing floating-point constants (r215595).	2014-08-19 19:44:13 +00:00
XCore