Juergen Ributzka 68a4ab08b3 [FastISel][AArch64] Add target-specific lowering for logical operations. ... This change adds support for immediate and shift-left folding into logical operations. This fixes rdar://problem/18223183. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217118 91177308-0d34-0410-b5e6-96231b3b80d8		2014-09-04 01:29:18 +00:00
..
AArch64	[FastISel][AArch64] Add target-specific lowering for logical operations.	2014-09-04 01:29:18 +00:00
ARM	Missing test from r216989	2014-09-02 22:46:18 +00:00
CPP
Generic	Add a regression test to sanity check the PBQP allocator.	2014-09-03 18:04:10 +00:00
Hexagon	DebugInfo: Assert that any CU for which debug_loc lists are emitted, has at least one range.	2014-08-06 00:21:25 +00:00
Inputs
Mips	Replace -use-init-array with -use-ctors.	2014-09-02 13:54:53 +00:00
MSP430	Do not assume the value passed to memset is an i32.	2014-08-29 08:23:53 +00:00
NVPTX	[MachineSink] Use the real post dominator tree	2014-09-01 03:47:25 +00:00
PowerPC	Enable splitting indexing from loads with TargetConstants	2014-09-02 16:05:23 +00:00
R600	R600/SI: Try to keep i32 mul on SALU	2014-09-03 23:24:35 +00:00
SPARC
SystemZ
Thumb	Check-label a bit more specific	2014-09-03 13:32:08 +00:00
Thumb2	ARM / x86_64 varargs: Don't save regparms in prologue without va_start	2014-08-22 21:59:26 +00:00
X86	[x86] Teach the new vector shuffle lowering about the zero masking	2014-09-04 01:13:48 +00:00
XCore