llvm-6502/lib/CodeGen
Dale Johannesen 2d1ec73d94 Rewrite handling of DBG_VALUE; previous algorithm
didn't handle
X =
Y<dead> = use X
DBG_VALUE(X)
I was hoping to avoid this approach as it's slower,
but I don't think it can be done.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95996 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-12 18:40:17 +00:00
..
AsmPrinter Use .empty() instead of .size(). 2010-02-11 10:37:57 +00:00
PBQP * Updated the cost matrix normalization proceedure to better handle infinite costs. 2010-02-12 09:43:37 +00:00
SelectionDAG Use array_pod_sort instead of std::sort for improved code size. 2010-02-11 18:06:56 +00:00
AggressiveAntiDepBreaker.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
AggressiveAntiDepBreaker.h
AntiDepBreaker.h
BranchFolding.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
BranchFolding.h
CalcSpillWeights.cpp Remove duplicated #include. 2010-02-10 01:22:57 +00:00
CMakeLists.txt Add a new pass on machine instructions to optimize away PHI cycles that 2010-02-12 01:30:21 +00:00
CodePlacementOpt.cpp Fix several comments which had previously been "the the" where a 2010-02-10 20:04:19 +00:00
CriticalAntiDepBreaker.cpp
CriticalAntiDepBreaker.h
DeadMachineInstructionElim.cpp Rewrite handling of DBG_VALUE; previous algorithm 2010-02-12 18:40:17 +00:00
DwarfEHPrepare.cpp
ELF.h
ELFCodeEmitter.cpp
ELFCodeEmitter.h
ELFWriter.cpp remove dead #include, stupid symlinks. 2010-02-02 22:37:42 +00:00
ELFWriter.h
ExactHazardRecognizer.cpp Fix "the the" and similar typos. 2010-02-10 16:03:48 +00:00
ExactHazardRecognizer.h
GCMetadata.cpp
GCMetadataPrinter.cpp
GCStrategy.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
IfConversion.cpp
IntrinsicLowering.cpp
LatencyPriorityQueue.cpp
LiveInterval.cpp
LiveIntervalAnalysis.cpp When I rewrote this loop per Chris' preference I 2010-02-10 21:41:41 +00:00
LiveStackAnalysis.cpp
LiveVariables.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
LLVMTargetMachine.cpp Reapply the new LoopStrengthReduction code, with compile time and 2010-02-12 10:34:29 +00:00
LowerSubregs.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
MachineBasicBlock.cpp Fix comments to reflect renaming elsewhere. 2010-02-10 00:11:11 +00:00
MachineDominators.cpp
MachineFunction.cpp Fix "the the" and similar typos. 2010-02-10 16:03:48 +00:00
MachineFunctionAnalysis.cpp
MachineFunctionPass.cpp
MachineInstr.cpp Fix "the the" and similar typos. 2010-02-10 16:03:48 +00:00
MachineLICM.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
MachineLoopInfo.cpp
MachineModuleInfo.cpp Fix an uninitialized value. Radar 7609421. 2010-02-06 05:55:20 +00:00
MachineModuleInfoImpls.cpp make MachineModuleInfoMachO hold non-const MCSymbol*'s instead 2010-02-03 06:18:30 +00:00
MachinePassRegistry.cpp
MachineRegisterInfo.cpp
MachineSink.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
MachineSSAUpdater.cpp fix missing #includes. 2010-02-10 01:17:36 +00:00
MachineVerifier.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
Makefile
ObjectCodeEmitter.cpp
OcamlGC.cpp
OptimizeExts.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
OptimizePHIs.cpp Add a new pass on machine instructions to optimize away PHI cycles that 2010-02-12 01:30:21 +00:00
Passes.cpp
PHIElimination.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
PHIElimination.h move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
PostRASchedulerList.cpp
PreAllocSplitting.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
ProcessImplicitDefs.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
PrologEpilogInserter.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
PrologEpilogInserter.h
PseudoSourceValue.cpp
README.txt
RegAllocLinearScan.cpp
RegAllocLocal.cpp Fix comments to reflect renaming elsewhere. 2010-02-10 00:11:11 +00:00
RegAllocPBQP.cpp Fixed a bug in the PBQP allocator's findCoalesces method. 2010-02-09 00:50:27 +00:00
RegisterCoalescer.cpp
RegisterScavenging.cpp
ScheduleDAG.cpp
ScheduleDAGEmit.cpp
ScheduleDAGInstrs.cpp
ScheduleDAGInstrs.h
ScheduleDAGPrinter.cpp
ShadowStackGC.cpp
ShrinkWrapping.cpp
SimpleHazardRecognizer.h
SimpleRegisterCoalescing.cpp Reapply coalescer fix for better cross-class coalescing. 2010-02-11 23:55:29 +00:00
SimpleRegisterCoalescing.h
SjLjEHPrepare.cpp Update of 94055 to track the IR level call site information via an intrinsic. 2010-01-28 01:45:32 +00:00
SlotIndexes.cpp Fix "the the" and similar typos. 2010-02-10 16:03:48 +00:00
Spiller.cpp
Spiller.h
StackProtector.cpp
StackSlotColoring.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
StrongPHIElimination.cpp Fix "the the" and similar typos. 2010-02-10 16:03:48 +00:00
TailDuplication.cpp Reuse operand location when updating PHI instructions. 2010-02-11 00:34:33 +00:00
TargetInstrInfoImpl.cpp
TwoAddressInstructionPass.cpp Don't allow DBG_VALUE to affect codegen. 2010-02-11 18:22:31 +00:00
UnreachableBlockElim.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
VirtRegMap.cpp Fix "the the" and similar typos. 2010-02-10 16:03:48 +00:00
VirtRegMap.h
VirtRegRewriter.cpp fix a layering violation: VirtRegRewriter.cpp shouldn't use AsmPrinter.h. 2010-02-10 01:23:18 +00:00
VirtRegRewriter.h

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvments:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.