llvm-6502/test/CodeGen
Chandler Carruth 699fd1909e [x86] Teach the new vector shuffle lowering about the simplest of
'insertps' patterns.

This replaces two shuffles with a single insertps in very common cases.
My next patch will extend this to leverage the zeroing capabilities of
insertps which will allow it to be used in a much wider set of cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217100 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-03 22:48:34 +00:00
..
AArch64 Reapply r216805 "[MachineCombiner][AArch64] Use the correct register class for MADD, SUB, and OR."" 2014-09-03 07:07:10 +00:00
ARM Missing test from r216989 2014-09-02 22:46:18 +00:00
CPP
Generic Add a regression test to sanity check the PBQP allocator. 2014-09-03 18:04:10 +00:00
Hexagon
Inputs
Mips Replace -use-init-array with -use-ctors. 2014-09-02 13:54:53 +00:00
MSP430
NVPTX [MachineSink] Use the real post dominator tree 2014-09-01 03:47:25 +00:00
PowerPC Enable splitting indexing from loads with TargetConstants 2014-09-02 16:05:23 +00:00
R600 R600/SI: Add a pattern for i64 and in a branch 2014-09-03 15:22:41 +00:00
SPARC
SystemZ
Thumb Check-label a bit more specific 2014-09-03 13:32:08 +00:00
Thumb2
X86 [x86] Teach the new vector shuffle lowering about the simplest of 2014-09-03 22:48:34 +00:00
XCore