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Bill Wendling 69a05a7b92 Generate a VTBL instruction instead of a series of loads and stores when we
can. As Nate pointed out, VTBL isn't super performant, but it *has* to be better
than this:

_shuf:
@ BB#0:       @ %entry
  push        {r4, r7, lr}
  add         r7, sp, 
  sub         sp, 
  mov         r4, sp
  bic         r4, r4, 
  mov         sp, r4
  mov         r2, sp
  vmov        d16, r0, r1
  orr         r0, r2, 
  orr         r3, r2, 
  vst1.8      {d16[0]}, [r3]
  vst1.8      {d16[5]}, [r0]
  subs        r4, r7, 
  orr         r0, r2, 
  vst1.8      {d16[4]}, [r0]
  orr         r0, r2, 
  vst1.8      {d16[4]}, [r0]
  orr         r0, r2, 
  vst1.8      {d16[0]}, [r0]
  orr         r0, r2, 
  vst1.8      {d16[2]}, [r0]
  orr         r0, r2, 
  vst1.8      {d16[1]}, [r0]
  vst1.8      {d16[3]}, [r2]
  vldr.64     d16, [sp]
  vmov        r0, r1, d16
  mov         sp, r4
  pop         {r4, r7, pc}

The "illegal" testcase in vext.ll is no longer illegal.
<rdar://problem/9078775>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127630 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 23:02:38 +00:00
..
2011-03-10 00:51:01 +00:00
2011-03-12 22:01:42 +00:00