mirror of
https://github.com/c64scene-ar/llvm-6502.git
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8b6a20accd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90109 91177308-0d34-0410-b5e6-96231b3b80d8
155 lines
3.8 KiB
LLVM
155 lines
3.8 KiB
LLVM
; RUN: llc < %s -disable-mmx -march=x86-64 -mattr=+sse42 | FileCheck %s
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; Verify when widening a divide/remainder operation, we only generate a
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; divide/rem per element since divide/remainder can trap.
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define void @vectorDiv (<2 x i32> addrspace(1)* %nsource, <2 x i32> addrspace(1)* %dsource, <2 x i32> addrspace(1)* %qdest) nounwind {
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; CHECK: idivl
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; CHECK: idivl
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; CHECK-NOT: idivl
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; CHECK: ret
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entry:
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%nsource.addr = alloca <2 x i32> addrspace(1)*, align 4
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%dsource.addr = alloca <2 x i32> addrspace(1)*, align 4
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%qdest.addr = alloca <2 x i32> addrspace(1)*, align 4
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%index = alloca i32, align 4
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store <2 x i32> addrspace(1)* %nsource, <2 x i32> addrspace(1)** %nsource.addr
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store <2 x i32> addrspace(1)* %dsource, <2 x i32> addrspace(1)** %dsource.addr
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store <2 x i32> addrspace(1)* %qdest, <2 x i32> addrspace(1)** %qdest.addr
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%tmp = load <2 x i32> addrspace(1)** %qdest.addr
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%tmp1 = load i32* %index
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%arrayidx = getelementptr <2 x i32> addrspace(1)* %tmp, i32 %tmp1
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%tmp2 = load <2 x i32> addrspace(1)** %nsource.addr
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%tmp3 = load i32* %index
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%arrayidx4 = getelementptr <2 x i32> addrspace(1)* %tmp2, i32 %tmp3
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%tmp5 = load <2 x i32> addrspace(1)* %arrayidx4
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%tmp6 = load <2 x i32> addrspace(1)** %dsource.addr
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%tmp7 = load i32* %index
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%arrayidx8 = getelementptr <2 x i32> addrspace(1)* %tmp6, i32 %tmp7
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%tmp9 = load <2 x i32> addrspace(1)* %arrayidx8
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%tmp10 = sdiv <2 x i32> %tmp5, %tmp9
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store <2 x i32> %tmp10, <2 x i32> addrspace(1)* %arrayidx
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ret void
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}
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define <3 x i8> @test_char_div(<3 x i8> %num, <3 x i8> %div) {
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; CHECK: idivb
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; CHECK: idivb
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; CHECK: idivb
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; CHECK-NOT: idivb
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; CHECK: ret
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%div.r = sdiv <3 x i8> %num, %div
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ret <3 x i8> %div.r
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}
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define <3 x i8> @test_uchar_div(<3 x i8> %num, <3 x i8> %div) {
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; CHECK: divb
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; CHECK: divb
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; CHECK: divb
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; CHECK-NOT: divb
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; CHECK: ret
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%div.r = udiv <3 x i8> %num, %div
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ret <3 x i8> %div.r
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}
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define <5 x i16> @test_short_div(<5 x i16> %num, <5 x i16> %div) {
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; CHECK: idivw
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; CHECK: idivw
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; CHECK: idivw
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; CHECK: idivw
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; CHECK: idivw
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; CHECK-NOT: idivw
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; CHECK: ret
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%div.r = sdiv <5 x i16> %num, %div
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ret <5 x i16> %div.r
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}
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define <4 x i16> @test_ushort_div(<4 x i16> %num, <4 x i16> %div) {
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; CHECK: divw
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; CHECK: divw
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; CHECK: divw
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; CHECK: divw
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; CHECK-NOT: divw
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; CHECK: ret
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%div.r = udiv <4 x i16> %num, %div
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ret <4 x i16> %div.r
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}
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define <3 x i32> @test_uint_div(<3 x i32> %num, <3 x i32> %div) {
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; CHECK: divl
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; CHECK: divl
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; CHECK: divl
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; CHECK-NOT: divl
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; CHECK: ret
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%div.r = udiv <3 x i32> %num, %div
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ret <3 x i32> %div.r
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}
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define <3 x i64> @test_long_div(<3 x i64> %num, <3 x i64> %div) {
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; CHECK: idivq
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; CHECK: idivq
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; CHECK: idivq
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; CHECK-NOT: idivq
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; CHECK: ret
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%div.r = sdiv <3 x i64> %num, %div
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ret <3 x i64> %div.r
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}
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define <3 x i64> @test_ulong_div(<3 x i64> %num, <3 x i64> %div) {
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; CHECK: divq
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; CHECK: divq
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; CHECK: divq
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; CHECK-NOT: divq
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; CHECK: ret
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%div.r = udiv <3 x i64> %num, %div
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ret <3 x i64> %div.r
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}
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define <4 x i8> @test_char_rem(<4 x i8> %num, <4 x i8> %rem) {
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; CHECK: idivb
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; CHECK: idivb
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; CHECK: idivb
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; CHECK: idivb
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; CHECK-NOT: idivb
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; CHECK: ret
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%rem.r = srem <4 x i8> %num, %rem
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ret <4 x i8> %rem.r
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}
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define <5 x i16> @test_short_rem(<5 x i16> %num, <5 x i16> %rem) {
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; CHECK: idivw
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; CHECK: idivw
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; CHECK: idivw
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; CHECK: idivw
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; CHECK: idivw
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; CHECK-NOT: idivw
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; CHECK: ret
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%rem.r = srem <5 x i16> %num, %rem
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ret <5 x i16> %rem.r
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}
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define <4 x i32> @test_uint_rem(<4 x i32> %num, <4 x i32> %rem) {
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; CHECK: idivl
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; CHECK: idivl
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; CHECK: idivl
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; CHECK: idivl
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; CHECK-NOT: idivl
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; CHECK: ret
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%rem.r = srem <4 x i32> %num, %rem
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ret <4 x i32> %rem.r
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}
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define <5 x i64> @test_ulong_rem(<5 x i64> %num, <5 x i64> %rem) {
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; CHECK: divq
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; CHECK: divq
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; CHECK: divq
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; CHECK: divq
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; CHECK: divq
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; CHECK-NOT: divq
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; CHECK: ret
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%rem.r = urem <5 x i64> %num, %rem
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ret <5 x i64> %rem.r
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}
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