Tim Northover 6a04ef99f6 ARM64: extract a 32-bit subreg when selecting an inreg extend ... After the load/store refactoring, we were sometimes trying to feed a GPR64 into a 32-bit register offset operand. This failed in copyPhysReg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209566 91177308-0d34-0410-b5e6-96231b3b80d8		2014-05-24 07:05:42 +00:00
..
AsmParser	ARM64: model pre/post-indexed operations properly.	2014-05-22 11:56:20 +00:00
Disassembler	ARM64: model pre/post-indexed operations properly.	2014-05-22 11:56:20 +00:00
InstPrinter	ARM64: remove '#' from annotation of add/sub immediate	2014-05-22 14:20:05 +00:00
MCTargetDesc	ARM64: separate load/store operands to simplify assembler	2014-05-22 11:56:09 +00:00
TargetInfo
Utils
ARM64.h
ARM64.td
ARM64AddressTypePromotion.cpp
ARM64AdvSIMDScalarPass.cpp
ARM64AsmPrinter.cpp	ARM64: model pre/post-indexed operations properly.	2014-05-22 11:56:20 +00:00
ARM64BranchRelaxation.cpp	[ARM64] Split tbz/tbnz into W/X register variant	2014-05-19 15:58:15 +00:00
ARM64CallingConv.h
ARM64CallingConvention.td
ARM64CleanupLocalDynamicTLSPass.cpp
ARM64CollectLOH.cpp
ARM64ConditionalCompares.cpp
ARM64DeadRegisterDefinitionsPass.cpp
ARM64ExpandPseudoInsts.cpp
ARM64FastISel.cpp	Delete getAliasedGlobal.	2014-05-16 22:37:03 +00:00
ARM64FrameLowering.cpp	ARM64: model pre/post-indexed operations properly.	2014-05-22 11:56:20 +00:00
ARM64FrameLowering.h
ARM64InstrAtomics.td	ARM64: separate load/store operands to simplify assembler	2014-05-22 11:56:09 +00:00
ARM64InstrFormats.td	ARM64: model pre/post-indexed operations properly.	2014-05-22 11:56:20 +00:00
ARM64InstrInfo.cpp	ARM64: model pre/post-indexed operations properly.	2014-05-22 11:56:20 +00:00
ARM64InstrInfo.h	[ARM64] Adds Cortex-A53 scheduling support for vector load/store post.	2014-05-19 22:59:51 +00:00
ARM64InstrInfo.td	ARM64: these work too	2014-05-22 12:14:49 +00:00
ARM64ISelDAGToDAG.cpp	ARM64: extract a 32-bit subreg when selecting an inreg extend	2014-05-24 07:05:42 +00:00
ARM64ISelLowering.cpp	[ARM64] Fix a bug in shuffle vector lowering to generate corect vext ISD with swapped input vectors.	2014-05-23 02:54:50 +00:00
ARM64ISelLowering.h	Revert "Implement global merge optimization for global variables."	2014-05-16 13:02:18 +00:00
ARM64LoadStoreOptimizer.cpp	ARM64: model pre/post-indexed operations properly.	2014-05-22 11:56:20 +00:00
ARM64MachineFunctionInfo.h	[ARM64] Support aggressive fastcc/tailcallopt breaking ABI by popping out argument stack from callee.	2014-05-15 01:33:17 +00:00
ARM64MCInstLower.cpp
ARM64MCInstLower.h
ARM64PerfectShuffle.h
ARM64PromoteConstant.cpp
ARM64RegisterInfo.cpp
ARM64RegisterInfo.h
ARM64RegisterInfo.td	ARM64: separate load/store operands to simplify assembler	2014-05-22 11:56:09 +00:00
ARM64SchedA53.td	[ARM64] Adds Cortex-A53 scheduling support for vector load/store post.	2014-05-19 22:59:51 +00:00
ARM64SchedCyclone.td	[ARM64] Increases the Sched Model accuracy for Cortex-A53.	2014-05-16 17:15:33 +00:00
ARM64Schedule.td	[ARM64] Adds Cortex-A53 scheduling support for vector load/store post.	2014-05-19 22:59:51 +00:00
ARM64SelectionDAGInfo.cpp	Target: remove old constructors for CallLoweringInfo	2014-05-17 21:50:17 +00:00
ARM64SelectionDAGInfo.h
ARM64StorePairSuppress.cpp	Sort includes.	2014-05-22 01:07:18 +00:00
ARM64Subtarget.cpp	Fix compilation issues.	2014-05-21 23:51:57 +00:00
ARM64Subtarget.h	Make early if conversion dependent upon the subtarget and add	2014-05-21 23:40:26 +00:00
ARM64TargetMachine.cpp	Make early if conversion dependent upon the subtarget and add	2014-05-21 23:40:26 +00:00
ARM64TargetMachine.h
ARM64TargetObjectFile.cpp
ARM64TargetObjectFile.h
ARM64TargetTransformInfo.cpp	Fix typo.	2014-05-22 01:21:44 +00:00
CMakeLists.txt
LLVMBuild.txt	Fix broken build	2014-05-09 18:06:22 +00:00
Makefile