Tim Northover 6a04ef99f6 ARM64: extract a 32-bit subreg when selecting an inreg extend ... After the load/store refactoring, we were sometimes trying to feed a GPR64 into a 32-bit register offset operand. This failed in copyPhysReg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209566 91177308-0d34-0410-b5e6-96231b3b80d8		2014-05-24 07:05:42 +00:00
..
AArch64	AArch64/ARM64: enable more AArch64 tests.	2014-05-22 07:40:55 +00:00
ARM	Segmented stacks: omit __morestack call when there's no frame.	2014-05-22 13:03:43 +00:00
ARM64	ARM64: extract a 32-bit subreg when selecting an inreg extend	2014-05-24 07:05:42 +00:00
CPP
Generic
Hexagon	reverting r209132	2014-05-19 16:22:11 +00:00
Inputs
Mips	Use alias linkage and visibility to decide tls access mode.	2014-05-23 19:16:56 +00:00
MSP430	Fix broken FileCheck prefixes	2014-05-23 19:06:24 +00:00
NVPTX
PowerPC	[PowerPC] PR19796: Also match ISD::TargetConstant in isIntS16Immediate	2014-05-20 17:20:34 +00:00
R600	R600: Try to convert BFE back to standard bit ops when possible.	2014-05-22 18:09:12 +00:00
SPARC	TableGen: fix operand counting for aliases	2014-05-16 09:42:04 +00:00
SystemZ
Thumb	Segmented stacks: omit __morestack call when there's no frame.	2014-05-22 13:03:43 +00:00
Thumb2	Fix the Load/Store optimization pass to work with Thumb1.	2014-05-16 14:14:30 +00:00
X86	Use alias linkage and visibility to decide tls access mode.	2014-05-23 19:16:56 +00:00
XCore