Benjamin Kramer 914f8c4825 When the legalizer is splitting vector shifts, the result may not have the right shift amount type. ... Fix that by adding a cast to the shift expander. This came up with vector shifts on sse-less X86 CPUs. <2 x i64> = shl <2 x i64> <2 x i64> -> i64,i64 = shl i64 i64; shl i64 i64 -> i32,i32,i32,i32 = shl_parts i32 i32 i64; shl_parts i32 i32 i64 Now we cast the last two i64s to the right type. Fixes the crash in PR14668. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173615 91177308-0d34-0410-b5e6-96231b3b80d8		2013-01-27 11:19:11 +00:00
..
ARM	Fixed the condition codes for the atomic64 min/umin code generation on ARM. If the sutraction of the higher 32 bit parts gives a 0 result, we need to do the store operation.	2013-01-25 10:39:49 +00:00
CPP
Generic
Hexagon
MBlaze
Mips	[mips] Set flag neverHasSideEffects flag on some of the floating point instructions.	2013-01-25 00:20:39 +00:00
MSP430
NVPTX
PowerPC
R600
SI
SPARC
Thumb
Thumb2	FileCheck-ify some grep tests	2013-01-25 22:11:46 +00:00
X86	When the legalizer is splitting vector shifts, the result may not have the right shift amount type.	2013-01-27 11:19:11 +00:00
XCore