llvm-6502/test/CodeGen
Elena Demikhovsky 78d824a9ff AVX-512: Added intrinsics for VCVT* instructions.
All SKX forms. All VCVT instructions for float/double/int/long types.

Differential Revision: http://reviews.llvm.org/D11343



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242877 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-22 08:56:00 +00:00
..
AArch64 AArch64: Add aditional Cyclone macroop fusion opportunities 2015-07-20 22:34:47 +00:00
AMDGPU AMDGPU/SI: Add VI patterns to select FLAT instructions for global memory ops 2015-07-20 14:28:41 +00:00
ARM [ARM] Define subtarget feature "reserve-r9", which is used to decide 2015-07-21 01:42:02 +00:00
BPF
CPP
Generic Targets: commonize some stack realignment code 2015-07-20 22:51:32 +00:00
Hexagon [Hexagon] Generate MUX from conditional transfers when dot-new not possible 2015-07-20 21:23:25 +00:00
Inputs
Mips
MIR MIR Serialization: Start serializing the CFI operands with .cfi_def_cfa_offset. 2015-07-21 22:28:27 +00:00
MSP430
NVPTX [BranchFolding] do not iterate the aliases of virtual registers 2015-07-22 04:16:52 +00:00
PowerPC [PPC64LE] More vector swap optimization TLC 2015-07-21 21:40:17 +00:00
SPARC
SystemZ
Thumb [ARM] Refactor the prologue/epilogue emission to be more robust. 2015-07-20 21:42:14 +00:00
Thumb2 ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2 2015-07-21 00:18:59 +00:00
WebAssembly
WinEH
X86 AVX-512: Added intrinsics for VCVT* instructions. 2015-07-22 08:56:00 +00:00
XCore