Vladimir Sukharev 0751793310 [ARM] Rename v8.1a from "extension" to "architecture" ... v8.1a is renamed to architecture, following current entity naming approach. Excess generic cpu is removed. Intended use: "generic" cpu with "v8.1a" subtarget feature Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8767 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233811 91177308-0d34-0410-b5e6-96231b3b80d8		2015-04-01 14:54:56 +00:00
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AArch64	[AArch64] Add v8.1a "Rounding Double Multiply Add/Subtract" extension	2015-03-31 13:15:48 +00:00
ARM	[ARM] Rename v8.1a from "extension" to "architecture"	2015-04-01 14:54:56 +00:00
AsmParser	Add support for .ifnes psuedo-op.	2015-03-18 14:20:54 +00:00
COFF	[opaque pointer type] Add textual IR support for explicit type parameter to gep operator	2015-03-13 18:20:45 +00:00
Disassembler	[SystemZ] Support transactional execution on zEC12	2015-04-01 12:51:43 +00:00
ELF	MC: For variable symbols, maintain MCSymbol::Section as a cache.	2015-03-30 20:41:21 +00:00
Hexagon	Expand MUX instructions early on Hexagon	2015-03-31 13:35:12 +00:00
MachO	MC: For variable symbols, maintain MCSymbol::Section as a cache.	2015-03-30 20:41:21 +00:00
Markup
Mips	[mips] [IAS] Add support for the XOR $reg,imm pseudo-instruction.	2015-03-17 13:17:44 +00:00
PowerPC	[PowerPC] Add asm parser support for bitmask forms of rotate-and-mask instructions	2015-03-28 19:42:41 +00:00
R600	R600/SI: Add a stub GCNTargetMachine	2015-01-06 18:00:21 +00:00
Sparc	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
SystemZ	[SystemZ] Support transactional execution on zEC12	2015-04-01 12:51:43 +00:00
X86	Fix the operand encoding in the test instruction.	2015-03-31 12:31:55 +00:00