llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-15 23:31:37 +00:00

History

Justin Holewinski 6b50a7d179 [NVPTX] Make sure we do not generate MULWIDE ISD nodes when optimizations are disabled

With optimizations disabled, we disable the isel patterns for mul.wide; but we
were still generating MULWIDE ISD nodes.  Now, we only try to generate MULWIDE
ISD nodes in DAGCombine if the optimization level is not zero.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213773 91177308-0d34-0410-b5e6-96231b3b80d8

2014-07-23 17:40:45 +00:00

Analysis

Make use of the align parameter attribute for all pointer arguments

2014-07-22 16:58:55 +00:00

AsmParser

Add a dereferenceable attribute

2014-07-18 15:51:28 +00:00

Bitcode

Add a dereferenceable attribute

2014-07-18 15:51:28 +00:00

CodeGen

[AArch64] Lower sdiv x, pow2 using add + select + shift.