mirror of
https://github.com/c64scene-ar/llvm-6502.git
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ec58d9f9dd
as the 64-bit PowerOpen ABI" (Reference http://www.linux-foundation.org/spec/ELF/ppc64/). Change all ELF tests to ELF32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35624 91177308-0d34-0410-b5e6-96231b3b80d8
557 lines
24 KiB
TableGen
557 lines
24 KiB
TableGen
//===- PPCInstr64Bit.td - The PowerPC 64-bit Support -------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the PowerPC 64-bit instructions. These patterns are used
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// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// 64-bit operands.
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//
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def s16imm64 : Operand<i64> {
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let PrintMethod = "printS16ImmOperand";
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}
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def u16imm64 : Operand<i64> {
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let PrintMethod = "printU16ImmOperand";
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}
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def symbolHi64 : Operand<i64> {
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let PrintMethod = "printSymbolHi";
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}
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def symbolLo64 : Operand<i64> {
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let PrintMethod = "printSymbolLo";
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}
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//===----------------------------------------------------------------------===//
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// 64-bit transformation functions.
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//
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def SHL64 : SDNodeXForm<imm, [{
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// Transformation function: 63 - imm
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return getI32Imm(63 - N->getValue());
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}]>;
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def SRL64 : SDNodeXForm<imm, [{
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// Transformation function: 64 - imm
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return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
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}]>;
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def HI32_48 : SDNodeXForm<imm, [{
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// Transformation function: shift the immediate value down into the low bits.
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return getI32Imm((unsigned short)(N->getValue() >> 32));
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}]>;
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def HI48_64 : SDNodeXForm<imm, [{
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// Transformation function: shift the immediate value down into the low bits.
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return getI32Imm((unsigned short)(N->getValue() >> 48));
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}]>;
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//===----------------------------------------------------------------------===//
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// Pseudo instructions.
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//
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def IMPLICIT_DEF_G8RC : Pseudo<(ops G8RC:$rD), "; IMPLICIT_DEF_G8RC $rD",
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[(set G8RC:$rD, (undef))]>;
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//===----------------------------------------------------------------------===//
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// Calls.
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//
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let Defs = [LR8] in
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def MovePCtoLR8 : Pseudo<(ops piclabel:$label), "bl $label", []>,
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PPC970_Unit_BRU;
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// Macho ABI Calls.
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let isCall = 1, noResults = 1, PPC970_Unit = 7,
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// All calls clobber the PPC64 non-callee saved registers.
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Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
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F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
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V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
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LR8,CTR8,
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CR0,CR1,CR5,CR6,CR7] in {
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// Convenient aliases for call instructions
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def BL8_Macho : IForm<18, 0, 1,
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(ops calltarget:$func, variable_ops),
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"bl $func", BrB, []>; // See Pat patterns below.
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def BLA8_Macho : IForm<18, 1, 1,
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(ops aaddr:$func, variable_ops),
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"bla $func", BrB, [(PPCcall_Macho (i64 imm:$func))]>;
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}
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// ELF 64 ABI Calls = Macho ABI Calls
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// Used to define BL8_ELF and BLA8_ELF
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let isCall = 1, noResults = 1, PPC970_Unit = 7,
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// All calls clobber the PPC64 non-callee saved registers.
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Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
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F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
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V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
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LR8,CTR8,
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CR0,CR1,CR5,CR6,CR7] in {
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// Convenient aliases for call instructions
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def BL8_ELF : IForm<18, 0, 1,
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(ops calltarget:$func, variable_ops),
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"bl $func", BrB, []>; // See Pat patterns below.
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def BLA8_ELF : IForm<18, 1, 1,
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(ops aaddr:$func, variable_ops),
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"bla $func", BrB, [(PPCcall_ELF (i64 imm:$func))]>;
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}
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// Calls
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def : Pat<(PPCcall_Macho (i64 tglobaladdr:$dst)),
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(BL8_Macho tglobaladdr:$dst)>;
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def : Pat<(PPCcall_Macho (i64 texternalsym:$dst)),
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(BL8_Macho texternalsym:$dst)>;
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def : Pat<(PPCcall_ELF (i64 tglobaladdr:$dst)),
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(BL8_ELF tglobaladdr:$dst)>;
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def : Pat<(PPCcall_ELF (i64 texternalsym:$dst)),
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(BL8_ELF texternalsym:$dst)>;
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//===----------------------------------------------------------------------===//
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// 64-bit SPR manipulation instrs.
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def MFCTR8 : XFXForm_1_ext<31, 339, 9, (ops G8RC:$rT), "mfctr $rT", SprMFSPR>,
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PPC970_DGroup_First, PPC970_Unit_FXU;
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let Pattern = [(PPCmtctr G8RC:$rS)] in {
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def MTCTR8 : XFXForm_7_ext<31, 467, 9, (ops G8RC:$rS), "mtctr $rS", SprMTSPR>,
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PPC970_DGroup_First, PPC970_Unit_FXU;
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}
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def DYNALLOC8 : Pseudo<(ops G8RC:$result, G8RC:$negsize, memri:$fpsi),
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"${:comment} DYNALLOC8 $result, $negsize, $fpsi",
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[(set G8RC:$result,
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(PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>,
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Imp<[X1],[X1]>;
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def MTLR8 : XFXForm_7_ext<31, 467, 8, (ops G8RC:$rS), "mtlr $rS", SprMTSPR>,
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PPC970_DGroup_First, PPC970_Unit_FXU;
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def MFLR8 : XFXForm_1_ext<31, 339, 8, (ops G8RC:$rT), "mflr $rT", SprMFSPR>,
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PPC970_DGroup_First, PPC970_Unit_FXU;
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//===----------------------------------------------------------------------===//
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// Fixed point instructions.
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//
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let PPC970_Unit = 1 in { // FXU Operations.
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// Copies, extends, truncates.
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def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
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"or $rA, $rS, $rB", IntGeneral,
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[]>;
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def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
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"or $rA, $rS, $rB", IntGeneral,
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[]>;
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def LI8 : DForm_2_r0<14, (ops G8RC:$rD, symbolLo64:$imm),
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"li $rD, $imm", IntGeneral,
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[(set G8RC:$rD, immSExt16:$imm)]>;
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def LIS8 : DForm_2_r0<15, (ops G8RC:$rD, symbolHi64:$imm),
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"lis $rD, $imm", IntGeneral,
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[(set G8RC:$rD, imm16ShiftedSExt:$imm)]>;
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// Logical ops.
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def NAND8: XForm_6<31, 476, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
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"nand $rA, $rS, $rB", IntGeneral,
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[(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>;
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def AND8 : XForm_6<31, 28, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
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"and $rA, $rS, $rB", IntGeneral,
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[(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>;
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def ANDC8: XForm_6<31, 60, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
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"andc $rA, $rS, $rB", IntGeneral,
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[(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>;
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def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
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"or $rA, $rS, $rB", IntGeneral,
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[(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
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def NOR8 : XForm_6<31, 124, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
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"nor $rA, $rS, $rB", IntGeneral,
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[(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>;
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def ORC8 : XForm_6<31, 412, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
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"orc $rA, $rS, $rB", IntGeneral,
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[(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>;
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def EQV8 : XForm_6<31, 284, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
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"eqv $rA, $rS, $rB", IntGeneral,
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[(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>;
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def XOR8 : XForm_6<31, 316, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
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"xor $rA, $rS, $rB", IntGeneral,
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[(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>;
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// Logical ops with immediate.
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def ANDIo8 : DForm_4<28, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
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"andi. $dst, $src1, $src2", IntGeneral,
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[(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>,
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isDOT;
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def ANDISo8 : DForm_4<29, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
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"andis. $dst, $src1, $src2", IntGeneral,
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[(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>,
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isDOT;
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def ORI8 : DForm_4<24, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
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"ori $dst, $src1, $src2", IntGeneral,
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[(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>;
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def ORIS8 : DForm_4<25, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
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"oris $dst, $src1, $src2", IntGeneral,
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[(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>;
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def XORI8 : DForm_4<26, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
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"xori $dst, $src1, $src2", IntGeneral,
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[(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>;
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def XORIS8 : DForm_4<27, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
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"xoris $dst, $src1, $src2", IntGeneral,
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[(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>;
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def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
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"add $rT, $rA, $rB", IntGeneral,
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[(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
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def ADDI8 : DForm_2<14, (ops G8RC:$rD, G8RC:$rA, s16imm64:$imm),
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"addi $rD, $rA, $imm", IntGeneral,
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[(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>;
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def ADDIS8 : DForm_2<15, (ops G8RC:$rD, G8RC:$rA, symbolHi64:$imm),
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"addis $rD, $rA, $imm", IntGeneral,
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[(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>;
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def SUBFIC8: DForm_2< 8, (ops G8RC:$rD, G8RC:$rA, s16imm64:$imm),
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"subfic $rD, $rA, $imm", IntGeneral,
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[(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>;
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def SUBF8 : XOForm_1<31, 40, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
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"subf $rT, $rA, $rB", IntGeneral,
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[(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>;
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def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
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"mulhd $rT, $rA, $rB", IntMulHW,
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[(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
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def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
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"mulhdu $rT, $rA, $rB", IntMulHWU,
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[(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
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def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, G8RC:$rA, G8RC:$rB),
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"cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
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def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, G8RC:$rA, G8RC:$rB),
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"cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
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def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, G8RC:$rA, s16imm:$imm),
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"cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
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def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, G8RC:$src1, u16imm:$src2),
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"cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
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def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, GPRC:$rB),
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"sld $rA, $rS, $rB", IntRotateD,
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[(set G8RC:$rA, (shl G8RC:$rS, GPRC:$rB))]>, isPPC64;
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def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, GPRC:$rB),
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"srd $rA, $rS, $rB", IntRotateD,
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[(set G8RC:$rA, (srl G8RC:$rS, GPRC:$rB))]>, isPPC64;
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def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, GPRC:$rB),
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"srad $rA, $rS, $rB", IntRotateD,
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[(set G8RC:$rA, (sra G8RC:$rS, GPRC:$rB))]>, isPPC64;
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def EXTSB8 : XForm_11<31, 954, (ops G8RC:$rA, G8RC:$rS),
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"extsb $rA, $rS", IntGeneral,
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[(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>;
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def EXTSH8 : XForm_11<31, 922, (ops G8RC:$rA, G8RC:$rS),
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"extsh $rA, $rS", IntGeneral,
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[(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>;
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def EXTSW : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS),
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"extsw $rA, $rS", IntGeneral,
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[(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
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/// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers.
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def EXTSW_32 : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
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"extsw $rA, $rS", IntGeneral,
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[(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64;
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def EXTSW_32_64 : XForm_11<31, 986, (ops G8RC:$rA, GPRC:$rS),
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"extsw $rA, $rS", IntGeneral,
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[(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64;
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def SRADI : XSForm_1<31, 413, (ops G8RC:$rA, G8RC:$rS, u6imm:$SH),
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"sradi $rA, $rS, $SH", IntRotateD,
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[(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64;
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def CNTLZD : XForm_11<31, 58, (ops G8RC:$rA, G8RC:$rS),
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"cntlzd $rA, $rS", IntGeneral,
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[(set G8RC:$rA, (ctlz G8RC:$rS))]>;
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def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
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"divd $rT, $rA, $rB", IntDivD,
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[(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
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PPC970_DGroup_First, PPC970_DGroup_Cracked;
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def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
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"divdu $rT, $rA, $rB", IntDivD,
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[(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
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PPC970_DGroup_First, PPC970_DGroup_Cracked;
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def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
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"mulld $rT, $rA, $rB", IntMulHD,
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[(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
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let isCommutable = 1 in {
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def RLDIMI : MDForm_1<30, 3,
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(ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
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"rldimi $rA, $rS, $SH, $MB", IntRotateD,
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[]>, isPPC64, RegConstraint<"$rSi = $rA">,
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NoEncode<"$rSi">;
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}
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// Rotate instructions.
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def RLDICL : MDForm_1<30, 0,
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(ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB),
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"rldicl $rA, $rS, $SH, $MB", IntRotateD,
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[]>, isPPC64;
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def RLDICR : MDForm_1<30, 1,
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(ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME),
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"rldicr $rA, $rS, $SH, $ME", IntRotateD,
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[]>, isPPC64;
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} // End FXU Operations.
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//===----------------------------------------------------------------------===//
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// Load/Store instructions.
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//
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// Sign extending loads.
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let isLoad = 1, PPC970_Unit = 2 in {
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def LHA8: DForm_1<42, (ops G8RC:$rD, memri:$src),
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"lha $rD, $src", LdStLHA,
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[(set G8RC:$rD, (sextloadi16 iaddr:$src))]>,
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PPC970_DGroup_Cracked;
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def LWA : DSForm_1<58, 2, (ops G8RC:$rD, memrix:$src),
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"lwa $rD, $src", LdStLWA,
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[(set G8RC:$rD, (sextloadi32 ixaddr:$src))]>, isPPC64,
|
|
PPC970_DGroup_Cracked;
|
|
def LHAX8: XForm_1<31, 343, (ops G8RC:$rD, memrr:$src),
|
|
"lhax $rD, $src", LdStLHA,
|
|
[(set G8RC:$rD, (sextloadi16 xaddr:$src))]>,
|
|
PPC970_DGroup_Cracked;
|
|
def LWAX : XForm_1<31, 341, (ops G8RC:$rD, memrr:$src),
|
|
"lwax $rD, $src", LdStLHA,
|
|
[(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
|
|
PPC970_DGroup_Cracked;
|
|
|
|
// Update forms.
|
|
def LHAU8 : DForm_1<43, (ops G8RC:$rD, ptr_rc:$ea_result, symbolLo:$disp,
|
|
ptr_rc:$rA),
|
|
"lhau $rD, $disp($rA)", LdStGeneral,
|
|
[]>, RegConstraint<"$rA = $ea_result">,
|
|
NoEncode<"$ea_result">;
|
|
// NO LWAU!
|
|
|
|
}
|
|
|
|
// Zero extending loads.
|
|
let isLoad = 1, PPC970_Unit = 2 in {
|
|
def LBZ8 : DForm_1<34, (ops G8RC:$rD, memri:$src),
|
|
"lbz $rD, $src", LdStGeneral,
|
|
[(set G8RC:$rD, (zextloadi8 iaddr:$src))]>;
|
|
def LHZ8 : DForm_1<40, (ops G8RC:$rD, memri:$src),
|
|
"lhz $rD, $src", LdStGeneral,
|
|
[(set G8RC:$rD, (zextloadi16 iaddr:$src))]>;
|
|
def LWZ8 : DForm_1<32, (ops G8RC:$rD, memri:$src),
|
|
"lwz $rD, $src", LdStGeneral,
|
|
[(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
|
|
|
|
def LBZX8 : XForm_1<31, 87, (ops G8RC:$rD, memrr:$src),
|
|
"lbzx $rD, $src", LdStGeneral,
|
|
[(set G8RC:$rD, (zextloadi8 xaddr:$src))]>;
|
|
def LHZX8 : XForm_1<31, 279, (ops G8RC:$rD, memrr:$src),
|
|
"lhzx $rD, $src", LdStGeneral,
|
|
[(set G8RC:$rD, (zextloadi16 xaddr:$src))]>;
|
|
def LWZX8 : XForm_1<31, 23, (ops G8RC:$rD, memrr:$src),
|
|
"lwzx $rD, $src", LdStGeneral,
|
|
[(set G8RC:$rD, (zextloadi32 xaddr:$src))]>;
|
|
|
|
|
|
// Update forms.
|
|
def LBZU8 : DForm_1<35, (ops G8RC:$rD, ptr_rc:$ea_result, memri:$addr),
|
|
"lbzu $rD, $addr", LdStGeneral,
|
|
[]>, RegConstraint<"$addr.reg = $ea_result">,
|
|
NoEncode<"$ea_result">;
|
|
def LHZU8 : DForm_1<41, (ops G8RC:$rD, ptr_rc:$ea_result, memri:$addr),
|
|
"lhzu $rD, $addr", LdStGeneral,
|
|
[]>, RegConstraint<"$addr.reg = $ea_result">,
|
|
NoEncode<"$ea_result">;
|
|
def LWZU8 : DForm_1<33, (ops G8RC:$rD, ptr_rc:$ea_result, memri:$addr),
|
|
"lwzu $rD, $addr", LdStGeneral,
|
|
[]>, RegConstraint<"$addr.reg = $ea_result">,
|
|
NoEncode<"$ea_result">;
|
|
}
|
|
|
|
|
|
// Full 8-byte loads.
|
|
let isLoad = 1, PPC970_Unit = 2 in {
|
|
def LD : DSForm_1<58, 0, (ops G8RC:$rD, memrix:$src),
|
|
"ld $rD, $src", LdStLD,
|
|
[(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64;
|
|
def LDX : XForm_1<31, 21, (ops G8RC:$rD, memrr:$src),
|
|
"ldx $rD, $src", LdStLD,
|
|
[(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
|
|
|
|
def LDU : DSForm_1<58, 1, (ops G8RC:$rD, ptr_rc:$ea_result, memrix:$addr),
|
|
"ldu $rD, $addr", LdStLD,
|
|
[]>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
|
|
NoEncode<"$ea_result">;
|
|
|
|
}
|
|
|
|
let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
|
|
// Truncating stores.
|
|
def STB8 : DForm_1<38, (ops G8RC:$rS, memri:$src),
|
|
"stb $rS, $src", LdStGeneral,
|
|
[(truncstorei8 G8RC:$rS, iaddr:$src)]>;
|
|
def STH8 : DForm_1<44, (ops G8RC:$rS, memri:$src),
|
|
"sth $rS, $src", LdStGeneral,
|
|
[(truncstorei16 G8RC:$rS, iaddr:$src)]>;
|
|
def STW8 : DForm_1<36, (ops G8RC:$rS, memri:$src),
|
|
"stw $rS, $src", LdStGeneral,
|
|
[(truncstorei32 G8RC:$rS, iaddr:$src)]>;
|
|
def STBX8 : XForm_8<31, 215, (ops G8RC:$rS, memrr:$dst),
|
|
"stbx $rS, $dst", LdStGeneral,
|
|
[(truncstorei8 G8RC:$rS, xaddr:$dst)]>,
|
|
PPC970_DGroup_Cracked;
|
|
def STHX8 : XForm_8<31, 407, (ops G8RC:$rS, memrr:$dst),
|
|
"sthx $rS, $dst", LdStGeneral,
|
|
[(truncstorei16 G8RC:$rS, xaddr:$dst)]>,
|
|
PPC970_DGroup_Cracked;
|
|
def STWX8 : XForm_8<31, 151, (ops G8RC:$rS, memrr:$dst),
|
|
"stwx $rS, $dst", LdStGeneral,
|
|
[(truncstorei32 G8RC:$rS, xaddr:$dst)]>,
|
|
PPC970_DGroup_Cracked;
|
|
// Normal 8-byte stores.
|
|
def STD : DSForm_1<62, 0, (ops G8RC:$rS, memrix:$dst),
|
|
"std $rS, $dst", LdStSTD,
|
|
[(store G8RC:$rS, ixaddr:$dst)]>, isPPC64;
|
|
def STDX : XForm_8<31, 149, (ops G8RC:$rS, memrr:$dst),
|
|
"stdx $rS, $dst", LdStSTD,
|
|
[(store G8RC:$rS, xaddr:$dst)]>, isPPC64,
|
|
PPC970_DGroup_Cracked;
|
|
}
|
|
|
|
let isStore = 1, PPC970_Unit = 2 in {
|
|
|
|
def STBU8 : DForm_1<38, (ops ptr_rc:$ea_res, G8RC:$rS,
|
|
symbolLo:$ptroff, ptr_rc:$ptrreg),
|
|
"stbu $rS, $ptroff($ptrreg)", LdStGeneral,
|
|
[(set ptr_rc:$ea_res,
|
|
(pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg,
|
|
iaddroff:$ptroff))]>,
|
|
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
|
|
def STHU8 : DForm_1<45, (ops ptr_rc:$ea_res, G8RC:$rS,
|
|
symbolLo:$ptroff, ptr_rc:$ptrreg),
|
|
"sthu $rS, $ptroff($ptrreg)", LdStGeneral,
|
|
[(set ptr_rc:$ea_res,
|
|
(pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg,
|
|
iaddroff:$ptroff))]>,
|
|
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
|
|
def STWU8 : DForm_1<37, (ops ptr_rc:$ea_res, G8RC:$rS,
|
|
symbolLo:$ptroff, ptr_rc:$ptrreg),
|
|
"stwu $rS, $ptroff($ptrreg)", LdStGeneral,
|
|
[(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg,
|
|
iaddroff:$ptroff))]>,
|
|
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
|
|
|
|
|
|
def STDU : DSForm_1<62, 1, (ops ptr_rc:$ea_res, G8RC:$rS,
|
|
s16immX4:$ptroff, ptr_rc:$ptrreg),
|
|
"stdu $rS, $ptroff($ptrreg)", LdStSTD,
|
|
[(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg,
|
|
iaddroff:$ptroff))]>,
|
|
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">,
|
|
isPPC64;
|
|
|
|
}
|
|
|
|
let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
|
|
|
|
def STDUX : XForm_8<31, 181, (ops G8RC:$rS, memrr:$dst),
|
|
"stdux $rS, $dst", LdStSTD,
|
|
[]>, isPPC64;
|
|
|
|
|
|
// STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
|
|
def STD_32 : DSForm_1<62, 0, (ops GPRC:$rT, memrix:$dst),
|
|
"std $rT, $dst", LdStSTD,
|
|
[(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64;
|
|
def STDX_32 : XForm_8<31, 149, (ops GPRC:$rT, memrr:$dst),
|
|
"stdx $rT, $dst", LdStSTD,
|
|
[(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64,
|
|
PPC970_DGroup_Cracked;
|
|
}
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Floating point instructions.
|
|
//
|
|
|
|
|
|
let PPC970_Unit = 3 in { // FPU Operations.
|
|
def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
|
|
"fcfid $frD, $frB", FPGeneral,
|
|
[(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
|
|
def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
|
|
"fctidz $frD, $frB", FPGeneral,
|
|
[(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instruction Patterns
|
|
//
|
|
|
|
// Extensions and truncates to/from 32-bit regs.
|
|
def : Pat<(i64 (zext GPRC:$in)),
|
|
(RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
|
|
def : Pat<(i64 (anyext GPRC:$in)),
|
|
(OR4To8 GPRC:$in, GPRC:$in)>;
|
|
def : Pat<(i32 (trunc G8RC:$in)),
|
|
(OR8To4 G8RC:$in, G8RC:$in)>;
|
|
|
|
// Extending loads with i64 targets.
|
|
def : Pat<(zextloadi1 iaddr:$src),
|
|
(LBZ8 iaddr:$src)>;
|
|
def : Pat<(zextloadi1 xaddr:$src),
|
|
(LBZX8 xaddr:$src)>;
|
|
def : Pat<(extloadi1 iaddr:$src),
|
|
(LBZ8 iaddr:$src)>;
|
|
def : Pat<(extloadi1 xaddr:$src),
|
|
(LBZX8 xaddr:$src)>;
|
|
def : Pat<(extloadi8 iaddr:$src),
|
|
(LBZ8 iaddr:$src)>;
|
|
def : Pat<(extloadi8 xaddr:$src),
|
|
(LBZX8 xaddr:$src)>;
|
|
def : Pat<(extloadi16 iaddr:$src),
|
|
(LHZ8 iaddr:$src)>;
|
|
def : Pat<(extloadi16 xaddr:$src),
|
|
(LHZX8 xaddr:$src)>;
|
|
def : Pat<(extloadi32 iaddr:$src),
|
|
(LWZ8 iaddr:$src)>;
|
|
def : Pat<(extloadi32 xaddr:$src),
|
|
(LWZX8 xaddr:$src)>;
|
|
|
|
// SHL/SRL
|
|
def : Pat<(shl G8RC:$in, (i32 imm:$imm)),
|
|
(RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
|
|
def : Pat<(srl G8RC:$in, (i32 imm:$imm)),
|
|
(RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
|
|
|
|
// Hi and Lo for Darwin Global Addresses.
|
|
def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
|
|
def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
|
|
def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
|
|
def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
|
|
def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
|
|
def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
|
|
def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)),
|
|
(ADDIS8 G8RC:$in, tglobaladdr:$g)>;
|
|
def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)),
|
|
(ADDIS8 G8RC:$in, tconstpool:$g)>;
|
|
def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)),
|
|
(ADDIS8 G8RC:$in, tjumptable:$g)>;
|