David Sehr 6c4265a541 The current X86 NOP padding uses one long NOP followed by the remainder in ... one-byte NOPs. If the processor actually executes those NOPs, as it sometimes does with aligned bundling, this can have a performance impact. From my micro-benchmarks run on my one machine, a 15-byte NOP followed by twelve one-byte NOPs is about 20% worse than a 15 followed by a 12. This patch changes NOP emission to emit as many 15-byte (the maximum) as possible followed by at most one shorter NOP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176464 91177308-0d34-0410-b5e6-96231b3b80d8		2013-03-05 00:02:23 +00:00
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AArch64	AArch64: Undo change to how test was run	2013-02-11 10:51:41 +00:00
ARM	ARM: permit full range of valid ADR immediates.	2013-02-27 16:43:09 +00:00
AsmParser	AsmParser: More generic support for integer type suffices.	2013-02-26 20:17:10 +00:00
COFF	[MC][COFF] Delay handling symbol aliases when writing	2013-01-29 22:10:07 +00:00
Disassembler	AArch64: remove post-encoder method from FCMP (immediate) instructions.	2013-02-28 14:46:14 +00:00
ELF	Rewrite a test to check actual output rather than intermediate implementation	2013-03-01 20:54:00 +00:00
MachO	Revert r15266. This fixes llvm.org/pr15266.	2013-02-14 16:23:08 +00:00
Markup
MBlaze
Mips	Mips specific standalone assembler addressing mode %hi and %lo.	2013-02-21 02:09:31 +00:00
PowerPC
X86	The current X86 NOP padding uses one long NOP followed by the remainder in	2013-03-05 00:02:23 +00:00