mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
83 lines
3.3 KiB
LLVM
83 lines
3.3 KiB
LLVM
; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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%"class.llvm::MachineOperand" = type { i8, [3 x i8], i64, i64*, i64 }
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; Function Attrs: nounwind
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define void @_ZN4llvm17ScheduleDAGInstrs14addPhysRegDepsEPNS_5SUnitEj() #0 align 2 {
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; If we were able to split out the indexing, the load with update should be
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; removed (resulting in a nearly-empty output).
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; CHECK-LABEL: @_ZN4llvm17ScheduleDAGInstrs14addPhysRegDepsEPNS_5SUnitEj
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; CHECK-NOT: lhzu
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entry:
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%0 = load %"class.llvm::MachineOperand"*, %"class.llvm::MachineOperand"** undef, align 8
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br i1 undef, label %_ZNK4llvm14MachineOperand6getRegEv.exit, label %cond.false.i123
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cond.false.i123: ; preds = %_ZN4llvm12MachineInstr10getOperandEj.exit
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unreachable
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_ZNK4llvm14MachineOperand6getRegEv.exit: ; preds = %_ZN4llvm12MachineInstr10getOperandEj.exit
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%IsDef.i = getelementptr inbounds %"class.llvm::MachineOperand", %"class.llvm::MachineOperand"* %0, i64 undef, i32 1
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%1 = bitcast [3 x i8]* %IsDef.i to i24*
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%bf.load.i = load i24, i24* %1, align 1
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%2 = and i24 %bf.load.i, 128
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br i1 undef, label %for.cond.cleanup, label %for.body.lr.ph
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for.body.lr.ph: ; preds = %_ZNK4llvm14MachineOperand6getRegEv.exit
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%3 = zext i24 %2 to i32
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br i1 undef, label %cond.false.i134, label %_ZNK4llvm18MCRegAliasIteratordeEv.exit
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for.cond.cleanup: ; preds = %_ZNK4llvm14MachineOperand6getRegEv.exit
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br i1 undef, label %_ZNK4llvm14MachineOperand5isDefEv.exit, label %cond.false.i129
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cond.false.i129: ; preds = %for.cond.cleanup
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unreachable
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_ZNK4llvm14MachineOperand5isDefEv.exit: ; preds = %for.cond.cleanup
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br i1 undef, label %_ZNK4llvm14MachineOperand6getRegEv.exit247, label %cond.false.i244
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cond.false.i134: ; preds = %for.body.lr.ph
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unreachable
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_ZNK4llvm18MCRegAliasIteratordeEv.exit: ; preds = %for.body.lr.ph
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unreachable
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cond.false.i244: ; preds = %_ZNK4llvm14MachineOperand5isDefEv.exit
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unreachable
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_ZNK4llvm14MachineOperand6getRegEv.exit247: ; preds = %_ZNK4llvm14MachineOperand5isDefEv.exit
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br i1 undef, label %if.then53, label %if.end55
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if.then53: ; preds = %_ZNK4llvm14MachineOperand6getRegEv.exit247
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unreachable
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if.end55: ; preds = %_ZNK4llvm14MachineOperand6getRegEv.exit247
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br i1 undef, label %_ZNK4llvm14MachineOperand6isDeadEv.exit262, label %cond.false.i257
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cond.false.i257: ; preds = %if.end55
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unreachable
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_ZNK4llvm14MachineOperand6isDeadEv.exit262: ; preds = %if.end55
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%bf.load.i259 = load i24, i24* %1, align 1
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br i1 undef, label %if.then57, label %if.else59
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if.then57: ; preds = %_ZNK4llvm14MachineOperand6isDeadEv.exit262
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unreachable
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if.else59: ; preds = %_ZNK4llvm14MachineOperand6isDeadEv.exit262
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br i1 undef, label %if.end89, label %if.then62
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if.then62: ; preds = %if.else59
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unreachable
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if.end89: ; preds = %if.else59
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unreachable
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}
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attributes #0 = { nounwind }
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