mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-13 20:32:21 +00:00
aa5c996eda
This the first of a series of patches to add CodeGen support exploiting the instructions of the z13 vector facility. This patch adds support for the native integer vector types (v16i8, v8i16, v4i32, v2i64). When the vector facility is present, we default to the new vector ABI. This is characterized by two major differences: - Vector types are passed/returned in vector registers (except for unnamed arguments of a variable-argument list function). - Vector types are at most 8-byte aligned. The reason for the choice of 8-byte vector alignment is that the hardware is able to efficiently load vectors at 8-byte alignment, and the ABI only guarantees 8-byte alignment of the stack pointer, so requiring any higher alignment for vectors would require dynamic stack re-alignment code. However, for compatibility with old code that may use vector types, when *not* using the vector facility, the old alignment rules (vector types are naturally aligned) remain in use. These alignment rules are not only implemented at the C language level (implemented in clang), but also at the LLVM IR level. This is done by selecting a different DataLayout string depending on whether the vector ABI is in effect or not. Based on a patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236521 91177308-0d34-0410-b5e6-96231b3b80d8
229 lines
6.8 KiB
LLVM
229 lines
6.8 KiB
LLVM
; Test v4i32 comparisons.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Test eq.
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define <4 x i32> @f1(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
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; CHECK-LABEL: f1:
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; CHECK: vceqf %v24, %v26, %v28
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; CHECK-NEXT: br %r14
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%cmp = icmp eq <4 x i32> %val1, %val2
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%ret = sext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test ne.
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define <4 x i32> @f2(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
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; CHECK-LABEL: f2:
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; CHECK: vceqf [[REG:%v[0-9]+]], %v26, %v28
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; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = icmp ne <4 x i32> %val1, %val2
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%ret = sext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test sgt.
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define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
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; CHECK-LABEL: f3:
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; CHECK: vchf %v24, %v26, %v28
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; CHECK-NEXT: br %r14
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%cmp = icmp sgt <4 x i32> %val1, %val2
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%ret = sext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test sge.
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define <4 x i32> @f4(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
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; CHECK-LABEL: f4:
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; CHECK: vchf [[REG:%v[0-9]+]], %v28, %v26
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; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = icmp sge <4 x i32> %val1, %val2
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%ret = sext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test sle.
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define <4 x i32> @f5(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
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; CHECK-LABEL: f5:
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; CHECK: vchf [[REG:%v[0-9]+]], %v26, %v28
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; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = icmp sle <4 x i32> %val1, %val2
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%ret = sext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test slt.
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define <4 x i32> @f6(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
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; CHECK-LABEL: f6:
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; CHECK: vchf %v24, %v28, %v26
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; CHECK-NEXT: br %r14
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%cmp = icmp slt <4 x i32> %val1, %val2
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%ret = sext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test ugt.
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define <4 x i32> @f7(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
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; CHECK-LABEL: f7:
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; CHECK: vchlf %v24, %v26, %v28
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; CHECK-NEXT: br %r14
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%cmp = icmp ugt <4 x i32> %val1, %val2
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%ret = sext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test uge.
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define <4 x i32> @f8(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
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; CHECK-LABEL: f8:
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; CHECK: vchlf [[REG:%v[0-9]+]], %v28, %v26
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; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = icmp uge <4 x i32> %val1, %val2
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%ret = sext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test ule.
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define <4 x i32> @f9(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
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; CHECK-LABEL: f9:
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; CHECK: vchlf [[REG:%v[0-9]+]], %v26, %v28
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; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = icmp ule <4 x i32> %val1, %val2
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%ret = sext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test ult.
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define <4 x i32> @f10(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
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; CHECK-LABEL: f10:
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; CHECK: vchlf %v24, %v28, %v26
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; CHECK-NEXT: br %r14
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%cmp = icmp ult <4 x i32> %val1, %val2
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%ret = sext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test eq selects.
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define <4 x i32> @f11(<4 x i32> %val1, <4 x i32> %val2,
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<4 x i32> %val3, <4 x i32> %val4) {
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; CHECK-LABEL: f11:
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; CHECK: vceqf [[REG:%v[0-9]+]], %v24, %v26
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; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = icmp eq <4 x i32> %val1, %val2
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%ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
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ret <4 x i32> %ret
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}
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; Test ne selects.
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define <4 x i32> @f12(<4 x i32> %val1, <4 x i32> %val2,
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<4 x i32> %val3, <4 x i32> %val4) {
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; CHECK-LABEL: f12:
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; CHECK: vceqf [[REG:%v[0-9]+]], %v24, %v26
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; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = icmp ne <4 x i32> %val1, %val2
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%ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
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ret <4 x i32> %ret
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}
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; Test sgt selects.
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define <4 x i32> @f13(<4 x i32> %val1, <4 x i32> %val2,
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<4 x i32> %val3, <4 x i32> %val4) {
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; CHECK-LABEL: f13:
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; CHECK: vchf [[REG:%v[0-9]+]], %v24, %v26
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; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = icmp sgt <4 x i32> %val1, %val2
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%ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
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ret <4 x i32> %ret
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}
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; Test sge selects.
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define <4 x i32> @f14(<4 x i32> %val1, <4 x i32> %val2,
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<4 x i32> %val3, <4 x i32> %val4) {
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; CHECK-LABEL: f14:
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; CHECK: vchf [[REG:%v[0-9]+]], %v26, %v24
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; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = icmp sge <4 x i32> %val1, %val2
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%ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
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ret <4 x i32> %ret
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}
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; Test sle selects.
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define <4 x i32> @f15(<4 x i32> %val1, <4 x i32> %val2,
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<4 x i32> %val3, <4 x i32> %val4) {
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; CHECK-LABEL: f15:
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; CHECK: vchf [[REG:%v[0-9]+]], %v24, %v26
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; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = icmp sle <4 x i32> %val1, %val2
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%ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
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ret <4 x i32> %ret
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}
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; Test slt selects.
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define <4 x i32> @f16(<4 x i32> %val1, <4 x i32> %val2,
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<4 x i32> %val3, <4 x i32> %val4) {
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; CHECK-LABEL: f16:
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; CHECK: vchf [[REG:%v[0-9]+]], %v26, %v24
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; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = icmp slt <4 x i32> %val1, %val2
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%ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
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ret <4 x i32> %ret
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}
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; Test ugt selects.
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define <4 x i32> @f17(<4 x i32> %val1, <4 x i32> %val2,
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<4 x i32> %val3, <4 x i32> %val4) {
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; CHECK-LABEL: f17:
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; CHECK: vchlf [[REG:%v[0-9]+]], %v24, %v26
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; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = icmp ugt <4 x i32> %val1, %val2
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%ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
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ret <4 x i32> %ret
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}
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; Test uge selects.
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define <4 x i32> @f18(<4 x i32> %val1, <4 x i32> %val2,
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<4 x i32> %val3, <4 x i32> %val4) {
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; CHECK-LABEL: f18:
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; CHECK: vchlf [[REG:%v[0-9]+]], %v26, %v24
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; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = icmp uge <4 x i32> %val1, %val2
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%ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
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ret <4 x i32> %ret
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}
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; Test ule selects.
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define <4 x i32> @f19(<4 x i32> %val1, <4 x i32> %val2,
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<4 x i32> %val3, <4 x i32> %val4) {
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; CHECK-LABEL: f19:
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; CHECK: vchlf [[REG:%v[0-9]+]], %v24, %v26
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; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = icmp ule <4 x i32> %val1, %val2
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%ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
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ret <4 x i32> %ret
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}
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; Test ult selects.
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define <4 x i32> @f20(<4 x i32> %val1, <4 x i32> %val2,
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<4 x i32> %val3, <4 x i32> %val4) {
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; CHECK-LABEL: f20:
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; CHECK: vchlf [[REG:%v[0-9]+]], %v26, %v24
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; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = icmp ult <4 x i32> %val1, %val2
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%ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
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ret <4 x i32> %ret
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}
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