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https://github.com/c64scene-ar/llvm-6502.git
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dafa504341
* Added some Format 4 classes, but not instructions * Added notes on missing sections with FIXMEs * Added RDCCR instr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6388 91177308-0d34-0410-b5e6-96231b3b80d8
172 lines
3.8 KiB
C++
172 lines
3.8 KiB
C++
//===- Sparc.td - Target Description for Sparc V9 Target --------*- C++ -*-===//
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// vim:ft=cpp
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Format #3 classes
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//
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// F3 - Common superclass of all F3 instructions. All instructions have an op3
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// field.
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class F3 : InstV9 {
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bits<6> op3;
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set op{1} = 1; // Op = 2 or 3
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set Inst{24-19} = op3;
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}
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class F3_rd : F3 {
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bits<5> rd;
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set Inst{29-25} = rd;
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}
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class F3_rdsimm13 : F3_rd {
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bits<13> simm13;
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set Inst{12-0} = simm13;
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}
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class F3_rdsimm13rs1 : F3_rdsimm13 {
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bits<5> rs1;
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set Inst{18-14} = rs1;
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}
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// F3_rdrs1 - Common superclass of instructions that use rd & rs1
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class F3_rdrs1 : F3_rd {
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bits<5> rs1;
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set Inst{18-14} = rs1;
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}
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// F3_rs1rdrs2 - Common superclass of instructions with rd, rs1, & rs2 fields
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class F3_rdrs1rs2 : F3_rdrs1 {
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bits<5> rs2;
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set Inst{4-0} = rs2;
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}
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// F3_rs1 - Common class of instructions that do not have an rd field,
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// but start at rs1
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class F3_rs1 : F3 {
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bits<5> rs1;
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//set Inst{29-25} = dontcare;
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set Inst{18-14} = rs1;
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}
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// F3_rs1rs2 - Common class of instructions that only have rs1 and rs2 fields
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class F3_rs1rs2 : F3_rs1 {
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bits<5> rs2;
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//set Inst{12-5} = dontcare;
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set Inst{4-0} = rs2;
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}
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// F3_rs1simm13 - Common class of instructions that only have rs1 and simm13
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class F3_rs1simm13 : F3_rs1 {
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bits<13> simm13;
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set Inst{12-0} = simm13;
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}
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// Specific F3 classes...
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//
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class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3_rdrs1rs2 {
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set op = opVal;
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set op3 = op3val;
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set Name = name;
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set Inst{13} = 0; // i field = 0
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//set Inst{12-5} = dontcare;
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}
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class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3_rdsimm13rs1 {
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set op = opVal;
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set op3 = op3val;
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set Name = name;
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set Inst{13} = 1; // i field = 1
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}
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class F3_3<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rs2 {
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set op = opVal;
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set op3 = op3val;
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set Name = name;
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set Inst{13} = 0;
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}
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class F3_4<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1simm13 {
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bits<13> simm;
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set op = opVal;
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set op3 = op3Val;
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set Name = name;
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//set Inst{29-25} = dontcare;
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set Inst{13} = 1;
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set Inst{12-0} = simm;
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}
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class F3_11<bits<2> opVal, bits<6> op3Val, string name> : F3_rdrs1rs2 {
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bit x;
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set op = opVal;
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set op3 = op3Val;
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set Name = name;
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set Inst{13} = 0; // i field = 0
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set Inst{12} = x;
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//set Inst{11-5} = dontcare;
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}
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class F3_12<bits<2> opVal, bits<6> op3Val, string name> : F3 {
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bits<5> shcnt;
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set Name = name;
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set Inst{13} = 1; // i field = 1
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set Inst{12} = 0; // x field = 0
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//set Inst{11-5} = dontcare;
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set Inst{4-0} = shcnt;
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}
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class F3_13<bits<2> opVal, bits<6> op3Val, string name> : F3 {
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bits<6> shcnt;
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set Name = name;
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set Inst{13} = 1; // i field = 1
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set Inst{12} = 1; // x field = 1
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//set Inst{11-6} = dontcare;
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set Inst{5-0} = shcnt;
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}
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class F3_14<bits<2> opVal, bits<6> op3Val,
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bits<9> opfval, string name> : F3_rdrs1rs2 {
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set op = opVal;
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set op3 = op3Val;
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set Name = name;
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//set Inst{18-14} = dontcare;
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set Inst{13-5} = opfval;
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}
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class F3_16<bits<2> opVal, bits<6> op3Val,
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bits<9> opfval, string name> : F3_rdrs1rs2 {
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set op = opVal;
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set op3 = op3Val;
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set Name = name;
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set Inst{13-5} = opfval;
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}
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class F3_17<bits<2> opVal, bits<6> op3Val, string name> : F3_rdrs1 {
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set op = opVal;
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set op3 = op3Val;
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set Name = name;
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//Inst{13-0} = dontcare;
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}
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class F3_18<bits<5> fcn, string name> : F3 {
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set op = 2;
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set op3 = 0b111110;
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set Name = name;
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set Inst{29-25} = fcn;
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//set Inst{18-0 } = dontcare;
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}
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class F3_19<bits<2> opVal, bits<6> op3Val, string name> : F3_rd {
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set op = opVal;
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set op3 = op3Val;
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set Name = name;
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//Inst{18-0} = dontcare;
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}
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// FIXME: class F3_20
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// FIXME: class F3_21
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