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43600e95ec
It never does anything when running 'make check', and it get's in the way of updating live intervals in 2-addr. The hook was originally added to help form IT blocks in Thumb2 code before register allocation, but the pass ordering has changed since then, and we run if-conversion after register allocation now. When the MI scheduler is enabled, there will be no less than two schedulers between 2-addr and Thumb2ITBlockPass, so this hook is unlikely to help anything. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161794 91177308-0d34-0410-b5e6-96231b3b80d8
76 lines
2.8 KiB
C++
76 lines
2.8 KiB
C++
//===-- Thumb2InstrInfo.h - Thumb-2 Instruction Information -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Thumb-2 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef THUMB2INSTRUCTIONINFO_H
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#define THUMB2INSTRUCTIONINFO_H
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#include "ARM.h"
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#include "ARMBaseInstrInfo.h"
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#include "Thumb2RegisterInfo.h"
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namespace llvm {
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class ARMSubtarget;
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class ScheduleHazardRecognizer;
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class Thumb2InstrInfo : public ARMBaseInstrInfo {
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Thumb2RegisterInfo RI;
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public:
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explicit Thumb2InstrInfo(const ARMSubtarget &STI);
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/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
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void getNoopForMachoTarget(MCInst &NopInst) const;
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// Return the non-pre/post incrementing version of 'Opc'. Return 0
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// if there is not such an opcode.
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unsigned getUnindexedOpcode(unsigned Opc) const;
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void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
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MachineBasicBlock *NewDest) const;
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bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI) const;
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void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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const Thumb2RegisterInfo &getRegisterInfo() const { return RI; }
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};
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/// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical
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/// to llvm::getInstrPredicate except it returns AL for conditional branch
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/// instructions which are "predicated", but are not in IT blocks.
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ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
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}
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#endif // THUMB2INSTRUCTIONINFO_H
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