Matt Arsenault 6e5862cb8c R600/SI: Fix assertion on sign extend of 3 vectors ... This was trying to create an MVT with 3x vectors which created an invalid EVT git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222942 91177308-0d34-0410-b5e6-96231b3b80d8		2014-11-28 22:51:38 +00:00
..
AArch64	AArch64: treat [N x Ty] as a block during procedure calls.	2014-11-27 21:02:42 +00:00
ARM	Stop uppercasing build attribute data.	2014-11-27 12:13:56 +00:00
CPP
Generic
Hexagon	Handle ctor/init_array initialization.	2014-11-03 14:56:05 +00:00
Inputs
Mips	[mips][micromips] Use call instructions with short delay slots	2014-11-25 10:50:00 +00:00
MSP430
NVPTX	[NVPTX] Add NVPTXLowerStructArgs pass	2014-11-05 18:19:30 +00:00
PowerPC	[PowerPC] Implement combineRepeatedFPDivisors	2014-11-24 23:45:21 +00:00
R600	R600/SI: Fix assertion on sign extend of 3 vectors	2014-11-28 22:51:38 +00:00
SPARC
SystemZ
Thumb	[Thumb1] Re-write emitThumbRegPlusImmediate	2014-11-17 11:18:10 +00:00
Thumb2	ARM: allow constpool entry to be moved to the user's block in all cases.	2014-11-13 17:58:53 +00:00
X86	Revert "Masked Vector Load and Store Intrinsics."	2014-11-28 21:29:14 +00:00
XCore	Fix a bit of confusion about .set and produce more readable assembly.	2014-10-21 01:17:30 +00:00