mirror of
https://github.com/c64scene-ar/llvm-6502.git
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8eaed0f63d
This matches the format produced by the AMD proprietary driver.
//==================================================================//
// Shell script for converting .ll test cases: (Pass the .ll files
you want to convert to this script as arguments).
//==================================================================//
; This was necessary on my system so that A-Z in sed would match only
; upper case. I'm not sure why.
export LC_ALL='C'
TEST_FILES="$*"
MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r`
for f in $TEST_FILES; do
# Check that there are SI tests:
grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f
if [ $? -eq 0 ]; then
for match in $MATCHES; do
sed -i -e "s/\([ :]$match\)/\L\1/" $f
done
# Try to get check lines with partial instruction names
sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f
fi
done
sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll
sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll
sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll
sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll
sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll
//==================================================================//
// Shell script for converting .td files (run this last)
//==================================================================//
export LC_ALL='C'
sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td
sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221350 91177308-0d34-0410-b5e6-96231b3b80d8
76 lines
2.8 KiB
LLVM
76 lines
2.8 KiB
LLVM
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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declare i32 @llvm.r600.read.tidig.x() nounwind readnone
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; SI-LABEL: {{^}}uint_to_fp_f64_i32
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; SI: v_cvt_f64_u32_e32
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; SI: s_endpgm
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define void @uint_to_fp_f64_i32(double addrspace(1)* %out, i32 %in) {
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%cast = uitofp i32 %in to double
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store double %cast, double addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL: {{^}}uint_to_fp_i1_f64:
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; SI: v_cmp_eq_i32_e64 [[CMP:s\[[0-9]+:[0-9]\]]],
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; FIXME: We should the VGPR sources for V_CNDMASK are copied from SGPRs,
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; we should be able to fold the SGPRs into the V_CNDMASK instructions.
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; SI: v_cndmask_b32_e64 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CMP]]
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; SI: v_cndmask_b32_e64 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CMP]]
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; SI: buffer_store_dwordx2
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; SI: s_endpgm
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define void @uint_to_fp_i1_f64(double addrspace(1)* %out, i32 %in) {
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%cmp = icmp eq i32 %in, 0
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%fp = uitofp i1 %cmp to double
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store double %fp, double addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}uint_to_fp_i1_f64_load:
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; SI: v_cndmask_b32_e64 [[IRESULT:v[0-9]]], 0, 1
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; SI-NEXT: v_cvt_f64_u32_e32 [[RESULT:v\[[0-9]+:[0-9]\]]], [[IRESULT]]
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; SI: buffer_store_dwordx2 [[RESULT]]
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; SI: s_endpgm
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define void @uint_to_fp_i1_f64_load(double addrspace(1)* %out, i1 %in) {
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%fp = uitofp i1 %in to double
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store double %fp, double addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL: {{^}}v_uint_to_fp_i64_to_f64
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; SI: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
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; SI-DAG: v_cvt_f64_u32_e32 [[LO_CONV:v\[[0-9]+:[0-9]+\]]], v[[LO]]
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; SI-DAG: v_cvt_f64_u32_e32 [[HI_CONV:v\[[0-9]+:[0-9]+\]]], v[[HI]]
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; SI: v_ldexp_f64 [[LDEXP:v\[[0-9]+:[0-9]+\]]], [[HI_CONV]], 32
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; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[LDEXP]], [[LO_CONV]]
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; SI: buffer_store_dwordx2 [[RESULT]]
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define void @v_uint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 addrspace(1)* %in) {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep = getelementptr i64 addrspace(1)* %in, i32 %tid
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%val = load i64 addrspace(1)* %gep, align 8
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%result = uitofp i64 %val to double
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store double %result, double addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}s_uint_to_fp_f64_i64
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define void @s_uint_to_fp_f64_i64(double addrspace(1)* %out, i64 %in) {
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%cast = uitofp i64 %in to double
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store double %cast, double addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL: {{^}}s_uint_to_fp_v2f64_v2i64
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define void @s_uint_to_fp_v2f64_v2i64(<2 x double> addrspace(1)* %out, <2 x i64> %in) {
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%cast = uitofp <2 x i64> %in to <2 x double>
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store <2 x double> %cast, <2 x double> addrspace(1)* %out, align 16
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ret void
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}
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; SI-LABEL: {{^}}s_uint_to_fp_v4f64_v4i64
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define void @s_uint_to_fp_v4f64_v4i64(<4 x double> addrspace(1)* %out, <4 x i64> %in) {
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%cast = uitofp <4 x i64> %in to <4 x double>
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store <4 x double> %cast, <4 x double> addrspace(1)* %out, align 16
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ret void
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}
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