llvm-6502/lib/Target/Alpha
Bill Wendling 6ef781f3ce Final de-tabification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47663 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 06:33:05 +00:00
..
Alpha.h
Alpha.td
AlphaAsmPrinter.cpp Change "Name" to "AsmName" in the target register info. Gee, a refactoring tool 2008-02-26 21:11:01 +00:00
AlphaBranchSelector.cpp rename MachineInstr::setInstrDescriptor -> setDesc 2008-01-11 18:10:50 +00:00
AlphaCodeEmitter.cpp
AlphaInstrFormats.td llvm.memory.barrier, and impl for x86 and alpha 2008-02-16 01:24:58 +00:00
AlphaInstrInfo.cpp It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned. 2008-02-08 21:20:40 +00:00
AlphaInstrInfo.h Rename MRegisterInfo to TargetRegisterInfo. 2008-02-10 18:45:23 +00:00
AlphaInstrInfo.td Final de-tabification. 2008-02-27 06:33:05 +00:00
AlphaISelDAGToDAG.cpp Convert MaskedValueIsZero and all its users to use APInt. Also add 2008-02-25 21:11:39 +00:00
AlphaISelLowering.cpp Atomic op support. If any gcc test uses __sync builtins, it might start failing on archs that haven't implemented them yet 2008-02-21 06:45:13 +00:00
AlphaISelLowering.h Atomic op support. If any gcc test uses __sync builtins, it might start failing on archs that haven't implemented them yet 2008-02-21 06:45:13 +00:00
AlphaJITInfo.cpp
AlphaJITInfo.h
AlphaLLRP.cpp
AlphaRegisterInfo.cpp Rename PrintableName to Name. 2008-02-26 21:47:57 +00:00
AlphaRegisterInfo.h Rename MRegisterInfo to TargetRegisterInfo. 2008-02-10 18:45:23 +00:00
AlphaRegisterInfo.td
AlphaRelocations.h
AlphaSchedule.td
AlphaSubtarget.cpp
AlphaSubtarget.h
AlphaTargetAsmInfo.cpp
AlphaTargetAsmInfo.h Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
AlphaTargetMachine.cpp
AlphaTargetMachine.h Rename MRegisterInfo to TargetRegisterInfo. 2008-02-10 18:45:23 +00:00
Makefile
README.txt

***

add gcc builtins for alpha instructions


***

custom expand byteswap into nifty 
extract/insert/mask byte/word/longword/quadword low/high
sequences

***

see if any of the extract/insert/mask operations can be added

***

match more interesting things for cmovlbc cmovlbs (move if low bit clear/set)

***

lower srem and urem

remq(i,j):  i - (j * divq(i,j)) if j != 0
remqu(i,j): i - (j * divqu(i,j)) if j != 0
reml(i,j):  i - (j * divl(i,j)) if j != 0
remlu(i,j): i - (j * divlu(i,j)) if j != 0

***

add crazy vector instructions (MVI):

(MIN|MAX)(U|S)(B8|W4) min and max, signed and unsigned, byte and word
PKWB, UNPKBW pack/unpack word to byte
PKLB UNPKBL pack/unpack long to byte
PERR pixel error (sum accross bytes of bytewise abs(i8v8 a - i8v8 b))

cmpbytes bytewise cmpeq of i8v8 a and i8v8 b (not part of MVI extentions)

this has some good examples for other operations that can be synthesised well 
from these rather meager vector ops (such as saturating add).
http://www.alphalinux.org/docs/MVI-full.html