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https://github.com/c64scene-ar/llvm-6502.git
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d275e025d2
There are some operands which can take either immediates or registers and we were previously using different register class to distinguish between operands that could take immediates and those that could not. This patch switches to using RegisterOperands which should simplify the backend by reducing the number of register classes and also make it easier to implement the assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225662 91177308-0d34-0410-b5e6-96231b3b80d8
122 lines
4.7 KiB
C++
122 lines
4.7 KiB
C++
//===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief This file provides AMDGPU specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUMCTargetDesc.h"
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#include "AMDGPUMCAsmInfo.h"
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#include "SIDefines.h"
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#include "InstPrinter/AMDGPUInstPrinter.h"
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#include "llvm/MC/MCCodeGenInfo.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MachineLocation.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define GET_INSTRINFO_MC_DESC
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#include "AMDGPUGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_MC_DESC
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#include "AMDGPUGenSubtargetInfo.inc"
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#define GET_REGINFO_MC_DESC
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#include "AMDGPUGenRegisterInfo.inc"
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static MCInstrInfo *createAMDGPUMCInstrInfo() {
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MCInstrInfo *X = new MCInstrInfo();
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InitAMDGPUMCInstrInfo(X);
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return X;
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}
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static MCRegisterInfo *createAMDGPUMCRegisterInfo(StringRef TT) {
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MCRegisterInfo *X = new MCRegisterInfo();
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InitAMDGPUMCRegisterInfo(X, 0);
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return X;
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}
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static MCSubtargetInfo *createAMDGPUMCSubtargetInfo(StringRef TT, StringRef CPU,
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StringRef FS) {
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MCSubtargetInfo * X = new MCSubtargetInfo();
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InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS);
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return X;
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}
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static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(StringRef TT, Reloc::Model RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OL) {
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MCCodeGenInfo *X = new MCCodeGenInfo();
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X->InitMCCodeGenInfo(RM, CM, OL);
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return X;
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}
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static MCInstPrinter *createAMDGPUMCInstPrinter(const Target &T,
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unsigned SyntaxVariant,
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const MCAsmInfo &MAI,
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const MCInstrInfo &MII,
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const MCRegisterInfo &MRI,
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const MCSubtargetInfo &STI) {
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return new AMDGPUInstPrinter(MAI, MII, MRI);
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}
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static MCCodeEmitter *createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) {
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return createSIMCCodeEmitter(MCII, MRI, STI, Ctx);
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} else {
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return createR600MCCodeEmitter(MCII, MRI, STI);
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}
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}
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static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
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MCContext &Ctx, MCAsmBackend &MAB,
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raw_ostream &_OS, MCCodeEmitter *_Emitter,
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const MCSubtargetInfo &STI, bool RelaxAll) {
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return createELFStreamer(Ctx, MAB, _OS, _Emitter, false);
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}
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extern "C" void LLVMInitializeR600TargetMC() {
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RegisterMCAsmInfo<AMDGPUMCAsmInfo> Y(TheAMDGPUTarget);
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RegisterMCAsmInfo<AMDGPUMCAsmInfo> Z(TheGCNTarget);
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TargetRegistry::RegisterMCCodeGenInfo(TheAMDGPUTarget, createAMDGPUMCCodeGenInfo);
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TargetRegistry::RegisterMCCodeGenInfo(TheGCNTarget, createAMDGPUMCCodeGenInfo);
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TargetRegistry::RegisterMCInstrInfo(TheAMDGPUTarget, createAMDGPUMCInstrInfo);
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TargetRegistry::RegisterMCInstrInfo(TheGCNTarget, createAMDGPUMCInstrInfo);
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TargetRegistry::RegisterMCRegInfo(TheAMDGPUTarget, createAMDGPUMCRegisterInfo);
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TargetRegistry::RegisterMCRegInfo(TheGCNTarget, createAMDGPUMCRegisterInfo);
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TargetRegistry::RegisterMCSubtargetInfo(TheAMDGPUTarget, createAMDGPUMCSubtargetInfo);
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TargetRegistry::RegisterMCSubtargetInfo(TheGCNTarget, createAMDGPUMCSubtargetInfo);
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TargetRegistry::RegisterMCInstPrinter(TheAMDGPUTarget, createAMDGPUMCInstPrinter);
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TargetRegistry::RegisterMCInstPrinter(TheGCNTarget, createAMDGPUMCInstPrinter);
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TargetRegistry::RegisterMCCodeEmitter(TheAMDGPUTarget, createAMDGPUMCCodeEmitter);
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TargetRegistry::RegisterMCCodeEmitter(TheGCNTarget, createAMDGPUMCCodeEmitter);
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TargetRegistry::RegisterMCAsmBackend(TheAMDGPUTarget, createAMDGPUAsmBackend);
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TargetRegistry::RegisterMCAsmBackend(TheGCNTarget, createAMDGPUAsmBackend);
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TargetRegistry::RegisterMCObjectStreamer(TheAMDGPUTarget, createMCStreamer);
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TargetRegistry::RegisterMCObjectStreamer(TheGCNTarget, createMCStreamer);
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}
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