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a7603982db
The DSP instructions in the Thumb2 instruction set are an optional extension in the Cortex-M* archtitecture. When present, the implementation is considered an "ARMv7E-M implementation," and when not, an "ARMv7-M implementation." Add a subtarget feature hook for the v7e-m instructions and hook it up. The cortex-m3 cpu is an example of a v7m implementation, while the cortex-m4 is a v7e-m implementation. rdar://9572992 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134261 91177308-0d34-0410-b5e6-96231b3b80d8
25 lines
852 B
LLVM
25 lines
852 B
LLVM
; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2xtpk,+t2dsp | FileCheck %s
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@x = weak global i16 0 ; <i16*> [#uses=1]
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@y = weak global i16 0 ; <i16*> [#uses=0]
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define i32 @f1(i32 %y) {
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; CHECK: f1
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; CHECK: smulbt r0, r1, r0
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%tmp = load i16* @x ; <i16> [#uses=1]
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%tmp1 = add i16 %tmp, 2 ; <i16> [#uses=1]
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%tmp2 = sext i16 %tmp1 to i32 ; <i32> [#uses=1]
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%tmp3 = ashr i32 %y, 16 ; <i32> [#uses=1]
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%tmp4 = mul i32 %tmp2, %tmp3 ; <i32> [#uses=1]
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ret i32 %tmp4
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}
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define i32 @f2(i32 %x, i32 %y) {
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; CHECK: f2
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; CHECK: smultt r0, r1, r0
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%tmp1 = ashr i32 %x, 16 ; <i32> [#uses=1]
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%tmp3 = ashr i32 %y, 16 ; <i32> [#uses=1]
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%tmp4 = mul i32 %tmp3, %tmp1 ; <i32> [#uses=1]
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ret i32 %tmp4
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}
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