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https://github.com/c64scene-ar/llvm-6502.git
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1b91bcddd5
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133171 91177308-0d34-0410-b5e6-96231b3b80d8
76 lines
2.5 KiB
TableGen
76 lines
2.5 KiB
TableGen
//===- PTXRegisterInfo.td - PTX Register defs ----------------*- tblgen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the PTX register file
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//===----------------------------------------------------------------------===//
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class PTXReg<string n> : Register<n> {
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let Namespace = "PTX";
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}
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//===----------------------------------------------------------------------===//
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// Registers
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//===----------------------------------------------------------------------===//
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///===- Predicate Registers -----------------------------------------------===//
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def P0 : PTXReg<"p0">;
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def P1 : PTXReg<"p1">;
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def P2 : PTXReg<"p2">;
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def P3 : PTXReg<"p3">;
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def P4 : PTXReg<"p4">;
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def P5 : PTXReg<"p5">;
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def P6 : PTXReg<"p6">;
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def P7 : PTXReg<"p7">;
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///===- 16-bit Integer Registers ------------------------------------------===//
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def RH0 : PTXReg<"rh0">;
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def RH1 : PTXReg<"rh1">;
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def RH2 : PTXReg<"rh2">;
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def RH3 : PTXReg<"rh3">;
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def RH4 : PTXReg<"rh4">;
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def RH5 : PTXReg<"rh5">;
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def RH6 : PTXReg<"rh6">;
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def RH7 : PTXReg<"rh7">;
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///===- 32-bit Integer Registers ------------------------------------------===//
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def R0 : PTXReg<"r0">;
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def R1 : PTXReg<"r1">;
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def R2 : PTXReg<"r2">;
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def R3 : PTXReg<"r3">;
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def R4 : PTXReg<"r4">;
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def R5 : PTXReg<"r5">;
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def R6 : PTXReg<"r6">;
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def R7 : PTXReg<"r7">;
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///===- 64-bit Integer Registers ------------------------------------------===//
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def RD0 : PTXReg<"rd0">;
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def RD1 : PTXReg<"rd1">;
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def RD2 : PTXReg<"rd2">;
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def RD3 : PTXReg<"rd3">;
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def RD4 : PTXReg<"rd4">;
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def RD5 : PTXReg<"rd5">;
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def RD6 : PTXReg<"rd6">;
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def RD7 : PTXReg<"rd7">;
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//===----------------------------------------------------------------------===//
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// Register classes
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//===----------------------------------------------------------------------===//
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def RegPred : RegisterClass<"PTX", [i1], 8, (sequence "P%u", 0, 7)>;
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def RegI16 : RegisterClass<"PTX", [i16], 16, (sequence "RH%u", 0, 7)>;
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def RegI32 : RegisterClass<"PTX", [i32], 32, (sequence "R%u", 0, 7)>;
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def RegI64 : RegisterClass<"PTX", [i64], 64, (sequence "RD%u", 0, 7)>;
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def RegF32 : RegisterClass<"PTX", [f32], 32, (sequence "R%u", 0, 7)>;
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def RegF64 : RegisterClass<"PTX", [f64], 64, (sequence "RD%u", 0, 7)>;
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