Tilmann Scheller 70c9be77f7 [ARM] Make the assembler reject unpredictable pre/post-indexed ARM LDR instructions.
The ARM ARM prohibits LDR instructions with writeback into the destination register. With this commit this constraint is now enforced and we stop assembling LDR instructions with unpredictable behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214498 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 11:08:51 +00:00
..
2014-07-01 14:34:30 +00:00
2014-07-30 23:59:11 +00:00