Bradley Smith a37c8c026d [ARM64] Add diagnostics for expected arithmetic shifts ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208330 91177308-0d34-0410-b5e6-96231b3b80d8		2014-05-08 15:40:39 +00:00
..
AsmParser	[ARM64] Add diagnostics for expected arithmetic shifts	2014-05-08 15:40:39 +00:00
Disassembler	AArch64/ARM64: implement diagnosis of unpredictable loads & stores	2014-05-06 14:15:14 +00:00
InstPrinter	ARM64: refactor NEON post-indexed loads & stores (MC).	2014-05-02 14:54:21 +00:00
MCTargetDesc	AArch64/ARM64: implement remaining TLS relocations (purely MC).	2014-04-30 16:13:26 +00:00
TargetInfo
Utils	[ARM64] Conditionalize CPU specific system registers on subtarget features	2014-05-01 10:25:36 +00:00
ARM64.h
ARM64.td	Fix typo.	2014-05-05 21:50:57 +00:00
ARM64AddressTypePromotion.cpp
ARM64AdvSIMDScalarPass.cpp	[ARM64][fast-isel] Disable target specific optimizations at -O0. Functionally,	2014-05-07 16:41:55 +00:00
ARM64AsmPrinter.cpp	AArch64/ARM64: support indexed loads/stores on vector types.	2014-05-02 14:54:15 +00:00
ARM64BranchRelaxation.cpp
ARM64CallingConv.h
ARM64CallingConvention.td	[ARM64-BE] Implement the lane-twiddling logic at AAPCS boundaries for big endian.	2014-05-07 12:33:41 +00:00
ARM64CleanupLocalDynamicTLSPass.cpp
ARM64CollectLOH.cpp
ARM64ConditionalCompares.cpp	AArch64/ARM64: expunge CPSR from the sources	2014-04-30 13:14:14 +00:00
ARM64DeadRegisterDefinitionsPass.cpp
ARM64ExpandPseudoInsts.cpp
ARM64FastISel.cpp	[ARM64-BE] Teach fast-isel about how to set up sub-word stack arguments for big endian calls.	2014-05-08 12:53:50 +00:00
ARM64FrameLowering.cpp
ARM64FrameLowering.h
ARM64InstrAtomics.td
ARM64InstrFormats.td	[ARM64] Add diagnostics for expected arithmetic shifts	2014-05-08 15:40:39 +00:00
ARM64InstrInfo.cpp	AArch64/ARM64: expunge CPSR from the sources	2014-04-30 13:14:14 +00:00
ARM64InstrInfo.h	AArch64/ARM64: expunge CPSR from the sources	2014-04-30 13:14:14 +00:00
ARM64InstrInfo.td	[ARM64] Add diagnostics for expected arithmetic shifts	2014-05-08 15:40:39 +00:00
ARM64ISelDAGToDAG.cpp	AArch64/ARM64: Port NEON post-increment load/store with 2/3/4 vectors to ARM64 backend.	2014-05-08 07:38:13 +00:00
ARM64ISelLowering.cpp	AArch64/ARM64: Port NEON post-increment load/store with 2/3/4 vectors to ARM64 backend.	2014-05-08 07:38:13 +00:00
ARM64ISelLowering.h	AArch64/ARM64: Port NEON post-increment load/store with 2/3/4 vectors to ARM64 backend.	2014-05-08 07:38:13 +00:00
ARM64LoadStoreOptimizer.cpp	[ARM64][fast-isel] Disable target specific optimizations at -O0. Functionally,	2014-05-07 16:41:55 +00:00
ARM64MachineFunctionInfo.h
ARM64MCInstLower.cpp
ARM64MCInstLower.h
ARM64PerfectShuffle.h
ARM64PromoteConstant.cpp
ARM64RegisterInfo.cpp	AArch64/ARM64: expunge CPSR from the sources	2014-04-30 13:14:14 +00:00
ARM64RegisterInfo.h
ARM64RegisterInfo.td	AArch64/ARM64: expunge CPSR from the sources	2014-04-30 13:14:14 +00:00
ARM64SchedA53.td
ARM64SchedCyclone.td
ARM64Schedule.td
ARM64SelectionDAGInfo.cpp
ARM64SelectionDAGInfo.h
ARM64StorePairSuppress.cpp
ARM64Subtarget.cpp	[ARM64] Prefer generation of bzero on Darwin only	2014-05-01 13:11:59 +00:00
ARM64Subtarget.h
ARM64TargetMachine.cpp	[ARM64][fast-isel] Disable target specific optimizations at -O0. Functionally,	2014-05-07 16:41:55 +00:00
ARM64TargetMachine.h
ARM64TargetObjectFile.cpp
ARM64TargetObjectFile.h
ARM64TargetTransformInfo.cpp
CMakeLists.txt
LLVMBuild.txt
Makefile