Bill Wendling 70fcb6bf58 CellSPU doesn't appear to support fully the "ISD::ROTR" operation. The DAG ... combiner can now generate ROTR if the backend says that it can handle it. Cell SPU says this, but gets an error from code gen saying that it can't select ROTR. I'm xfailing this test until this can be fixed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55579 91177308-0d34-0410-b5e6-96231b3b80d8		2008-08-31 02:32:12 +00:00
..
and_ops_more.ll
and_ops.ll
call_indirect.ll	- Expand tabs to spaces.	2008-03-05 23:00:19 +00:00
call.ll
ctpop.ll
dg.exp	sabre brings to my attention that the 'tr' suffix is also obsolete	2008-05-20 21:00:03 +00:00
dp_farith.ll
eqv.ll
extract_elt.ll
fcmp.ll	- Expand tabs to spaces.	2008-03-05 23:00:19 +00:00
fdiv.ll	- Expand tabs to spaces.	2008-03-05 23:00:19 +00:00
fneg-fabs.ll
icmp8.ll
icmp16.ll	Add more patterns to match in the integer comparison test harnesses.	2008-03-20 00:51:36 +00:00
icmp32.ll
immed16.ll
immed32.ll
immed64.ll	Add necessary 64-bit support so that gcc frontend compiles (mostly). Current	2008-06-02 22:18:03 +00:00
int2fp.ll
intrinsics_branch.ll
intrinsics_float.ll	- Expand tabs to spaces.	2008-03-05 23:00:19 +00:00
intrinsics_logical.ll
mul_ops.ll
nand.ll
or_ops.ll
rotate_ops.ll	CellSPU doesn't appear to support fully the "ISD::ROTR" operation. The DAG	2008-08-31 02:32:12 +00:00
select_bits.ll
shift_ops.ll
sp_farith.ll
struct_1.ll
vec_const.ll
vecinsert.ll