mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158461 91177308-0d34-0410-b5e6-96231b3b80d8
1033 lines
41 KiB
C++
1033 lines
41 KiB
C++
//===---- ScheduleDAGInstrs.cpp - MachineInstr Rescheduling ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements the ScheduleDAGInstrs class, which implements re-scheduling
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// of MachineInstrs.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "sched-instrs"
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#include "llvm/Operator.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Analysis/ValueTracking.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/CodeGen/RegisterPressure.h"
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#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/SmallPtrSet.h"
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using namespace llvm;
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static cl::opt<bool> EnableAASchedMI("enable-aa-sched-mi", cl::Hidden,
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cl::ZeroOrMore, cl::init(false),
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cl::desc("Enable use of AA during MI GAD construction"));
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ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
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const MachineLoopInfo &mli,
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const MachineDominatorTree &mdt,
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bool IsPostRAFlag,
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LiveIntervals *lis)
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: ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()),
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InstrItins(mf.getTarget().getInstrItineraryData()), LIS(lis),
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IsPostRA(IsPostRAFlag), UnitLatencies(false), CanHandleTerminators(false),
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LoopRegs(MDT), FirstDbgValue(0) {
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assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals");
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DbgValues.clear();
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assert(!(IsPostRA && MRI.getNumVirtRegs()) &&
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"Virtual registers must be removed prior to PostRA scheduling");
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}
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/// getUnderlyingObjectFromInt - This is the function that does the work of
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/// looking through basic ptrtoint+arithmetic+inttoptr sequences.
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static const Value *getUnderlyingObjectFromInt(const Value *V) {
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do {
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if (const Operator *U = dyn_cast<Operator>(V)) {
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// If we find a ptrtoint, we can transfer control back to the
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// regular getUnderlyingObjectFromInt.
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if (U->getOpcode() == Instruction::PtrToInt)
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return U->getOperand(0);
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// If we find an add of a constant or a multiplied value, it's
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// likely that the other operand will lead us to the base
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// object. We don't have to worry about the case where the
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// object address is somehow being computed by the multiply,
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// because our callers only care when the result is an
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// identifibale object.
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if (U->getOpcode() != Instruction::Add ||
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(!isa<ConstantInt>(U->getOperand(1)) &&
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Operator::getOpcode(U->getOperand(1)) != Instruction::Mul))
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return V;
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V = U->getOperand(0);
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} else {
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return V;
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}
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assert(V->getType()->isIntegerTy() && "Unexpected operand type!");
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} while (1);
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}
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/// getUnderlyingObject - This is a wrapper around GetUnderlyingObject
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/// and adds support for basic ptrtoint+arithmetic+inttoptr sequences.
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static const Value *getUnderlyingObject(const Value *V) {
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// First just call Value::getUnderlyingObject to let it do what it does.
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do {
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V = GetUnderlyingObject(V);
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// If it found an inttoptr, use special code to continue climing.
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if (Operator::getOpcode(V) != Instruction::IntToPtr)
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break;
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const Value *O = getUnderlyingObjectFromInt(cast<User>(V)->getOperand(0));
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// If that succeeded in finding a pointer, continue the search.
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if (!O->getType()->isPointerTy())
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break;
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V = O;
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} while (1);
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return V;
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}
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/// getUnderlyingObjectForInstr - If this machine instr has memory reference
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/// information and it can be tracked to a normal reference to a known
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/// object, return the Value for that object. Otherwise return null.
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static const Value *getUnderlyingObjectForInstr(const MachineInstr *MI,
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const MachineFrameInfo *MFI,
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bool &MayAlias) {
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MayAlias = true;
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if (!MI->hasOneMemOperand() ||
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!(*MI->memoperands_begin())->getValue() ||
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(*MI->memoperands_begin())->isVolatile())
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return 0;
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const Value *V = (*MI->memoperands_begin())->getValue();
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if (!V)
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return 0;
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V = getUnderlyingObject(V);
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if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
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// For now, ignore PseudoSourceValues which may alias LLVM IR values
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// because the code that uses this function has no way to cope with
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// such aliases.
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if (PSV->isAliased(MFI))
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return 0;
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MayAlias = PSV->mayAlias(MFI);
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return V;
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}
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if (isIdentifiedObject(V))
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return V;
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return 0;
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}
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void ScheduleDAGInstrs::startBlock(MachineBasicBlock *bb) {
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BB = bb;
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LoopRegs.Deps.clear();
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if (MachineLoop *ML = MLI.getLoopFor(BB))
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if (BB == ML->getLoopLatch())
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LoopRegs.VisitLoop(ML);
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}
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void ScheduleDAGInstrs::finishBlock() {
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// Subclasses should no longer refer to the old block.
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BB = 0;
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}
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/// Initialize the map with the number of registers.
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void Reg2SUnitsMap::setRegLimit(unsigned Limit) {
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PhysRegSet.setUniverse(Limit);
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SUnits.resize(Limit);
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}
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/// Clear the map without deallocating storage.
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void Reg2SUnitsMap::clear() {
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for (const_iterator I = reg_begin(), E = reg_end(); I != E; ++I) {
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SUnits[*I].clear();
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}
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PhysRegSet.clear();
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}
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/// Initialize the DAG and common scheduler state for the current scheduling
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/// region. This does not actually create the DAG, only clears it. The
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/// scheduling driver may call BuildSchedGraph multiple times per scheduling
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/// region.
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void ScheduleDAGInstrs::enterRegion(MachineBasicBlock *bb,
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MachineBasicBlock::iterator begin,
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MachineBasicBlock::iterator end,
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unsigned endcount) {
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assert(bb == BB && "startBlock should set BB");
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RegionBegin = begin;
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RegionEnd = end;
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EndIndex = endcount;
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MISUnitMap.clear();
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// Check to see if the scheduler cares about latencies.
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UnitLatencies = forceUnitLatencies();
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ScheduleDAG::clearDAG();
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}
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/// Close the current scheduling region. Don't clear any state in case the
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/// driver wants to refer to the previous scheduling region.
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void ScheduleDAGInstrs::exitRegion() {
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// Nothing to do.
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}
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/// addSchedBarrierDeps - Add dependencies from instructions in the current
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/// list of instructions being scheduled to scheduling barrier by adding
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/// the exit SU to the register defs and use list. This is because we want to
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/// make sure instructions which define registers that are either used by
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/// the terminator or are live-out are properly scheduled. This is
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/// especially important when the definition latency of the return value(s)
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/// are too high to be hidden by the branch or when the liveout registers
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/// used by instructions in the fallthrough block.
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void ScheduleDAGInstrs::addSchedBarrierDeps() {
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MachineInstr *ExitMI = RegionEnd != BB->end() ? &*RegionEnd : 0;
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ExitSU.setInstr(ExitMI);
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bool AllDepKnown = ExitMI &&
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(ExitMI->isCall() || ExitMI->isBarrier());
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if (ExitMI && AllDepKnown) {
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// If it's a call or a barrier, add dependencies on the defs and uses of
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// instruction.
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for (unsigned i = 0, e = ExitMI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = ExitMI->getOperand(i);
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if (!MO.isReg() || MO.isDef()) continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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if (TRI->isPhysicalRegister(Reg))
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Uses[Reg].push_back(&ExitSU);
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else {
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assert(!IsPostRA && "Virtual register encountered after regalloc.");
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addVRegUseDeps(&ExitSU, i);
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}
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}
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} else {
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// For others, e.g. fallthrough, conditional branch, assume the exit
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// uses all the registers that are livein to the successor blocks.
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assert(Uses.empty() && "Uses in set before adding deps?");
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for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
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SE = BB->succ_end(); SI != SE; ++SI)
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for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
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E = (*SI)->livein_end(); I != E; ++I) {
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unsigned Reg = *I;
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if (!Uses.contains(Reg))
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Uses[Reg].push_back(&ExitSU);
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}
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}
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}
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/// MO is an operand of SU's instruction that defines a physical register. Add
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/// data dependencies from SU to any uses of the physical register.
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void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU,
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const MachineOperand &MO) {
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assert(MO.isDef() && "expect physreg def");
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// Ask the target if address-backscheduling is desirable, and if so how much.
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const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
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unsigned SpecialAddressLatency = ST.getSpecialAddressLatency();
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unsigned DataLatency = SU->Latency;
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for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
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Alias.isValid(); ++Alias) {
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if (!Uses.contains(*Alias))
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continue;
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std::vector<SUnit*> &UseList = Uses[*Alias];
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for (unsigned i = 0, e = UseList.size(); i != e; ++i) {
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SUnit *UseSU = UseList[i];
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if (UseSU == SU)
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continue;
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unsigned LDataLatency = DataLatency;
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// Optionally add in a special extra latency for nodes that
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// feed addresses.
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// TODO: Perhaps we should get rid of
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// SpecialAddressLatency and just move this into
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// adjustSchedDependency for the targets that care about it.
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if (SpecialAddressLatency != 0 && !UnitLatencies &&
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UseSU != &ExitSU) {
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MachineInstr *UseMI = UseSU->getInstr();
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const MCInstrDesc &UseMCID = UseMI->getDesc();
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int RegUseIndex = UseMI->findRegisterUseOperandIdx(*Alias);
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assert(RegUseIndex >= 0 && "UseMI doesn't use register!");
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if (RegUseIndex >= 0 &&
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(UseMI->mayLoad() || UseMI->mayStore()) &&
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(unsigned)RegUseIndex < UseMCID.getNumOperands() &&
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UseMCID.OpInfo[RegUseIndex].isLookupPtrRegClass())
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LDataLatency += SpecialAddressLatency;
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}
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// Adjust the dependence latency using operand def/use
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// information (if any), and then allow the target to
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// perform its own adjustments.
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SDep dep(SU, SDep::Data, LDataLatency, *Alias);
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if (!UnitLatencies) {
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unsigned Latency = computeOperandLatency(SU, UseSU, dep);
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dep.setLatency(Latency);
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ST.adjustSchedDependency(SU, UseSU, dep);
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}
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UseSU->addPred(dep);
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}
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}
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}
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/// addPhysRegDeps - Add register dependencies (data, anti, and output) from
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/// this SUnit to following instructions in the same scheduling region that
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/// depend the physical register referenced at OperIdx.
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void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
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const MachineInstr *MI = SU->getInstr();
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const MachineOperand &MO = MI->getOperand(OperIdx);
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// Optionally add output and anti dependencies. For anti
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// dependencies we use a latency of 0 because for a multi-issue
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// target we want to allow the defining instruction to issue
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// in the same cycle as the using instruction.
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// TODO: Using a latency of 1 here for output dependencies assumes
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// there's no cost for reusing registers.
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SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
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for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
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Alias.isValid(); ++Alias) {
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if (!Defs.contains(*Alias))
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continue;
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std::vector<SUnit *> &DefList = Defs[*Alias];
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for (unsigned i = 0, e = DefList.size(); i != e; ++i) {
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SUnit *DefSU = DefList[i];
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if (DefSU == &ExitSU)
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continue;
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if (DefSU != SU &&
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(Kind != SDep::Output || !MO.isDead() ||
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!DefSU->getInstr()->registerDefIsDead(*Alias))) {
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if (Kind == SDep::Anti)
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DefSU->addPred(SDep(SU, Kind, 0, /*Reg=*/*Alias));
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else {
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unsigned AOLat = TII->getOutputLatency(InstrItins, MI, OperIdx,
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DefSU->getInstr());
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DefSU->addPred(SDep(SU, Kind, AOLat, /*Reg=*/*Alias));
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}
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}
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}
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}
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if (!MO.isDef()) {
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// Either insert a new Reg2SUnits entry with an empty SUnits list, or
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// retrieve the existing SUnits list for this register's uses.
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// Push this SUnit on the use list.
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Uses[MO.getReg()].push_back(SU);
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}
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else {
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addPhysRegDataDeps(SU, MO);
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// Either insert a new Reg2SUnits entry with an empty SUnits list, or
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// retrieve the existing SUnits list for this register's defs.
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std::vector<SUnit *> &DefList = Defs[MO.getReg()];
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// If a def is going to wrap back around to the top of the loop,
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// backschedule it.
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if (!UnitLatencies && DefList.empty()) {
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LoopDependencies::LoopDeps::iterator I = LoopRegs.Deps.find(MO.getReg());
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if (I != LoopRegs.Deps.end()) {
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const MachineOperand *UseMO = I->second.first;
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unsigned Count = I->second.second;
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const MachineInstr *UseMI = UseMO->getParent();
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unsigned UseMOIdx = UseMO - &UseMI->getOperand(0);
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const MCInstrDesc &UseMCID = UseMI->getDesc();
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const TargetSubtargetInfo &ST =
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TM.getSubtarget<TargetSubtargetInfo>();
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unsigned SpecialAddressLatency = ST.getSpecialAddressLatency();
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// TODO: If we knew the total depth of the region here, we could
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// handle the case where the whole loop is inside the region but
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// is large enough that the isScheduleHigh trick isn't needed.
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if (UseMOIdx < UseMCID.getNumOperands()) {
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// Currently, we only support scheduling regions consisting of
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// single basic blocks. Check to see if the instruction is in
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// the same region by checking to see if it has the same parent.
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if (UseMI->getParent() != MI->getParent()) {
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unsigned Latency = SU->Latency;
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if (UseMCID.OpInfo[UseMOIdx].isLookupPtrRegClass())
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Latency += SpecialAddressLatency;
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// This is a wild guess as to the portion of the latency which
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// will be overlapped by work done outside the current
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// scheduling region.
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Latency -= std::min(Latency, Count);
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// Add the artificial edge.
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ExitSU.addPred(SDep(SU, SDep::Order, Latency,
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/*Reg=*/0, /*isNormalMemory=*/false,
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/*isMustAlias=*/false,
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/*isArtificial=*/true));
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} else if (SpecialAddressLatency > 0 &&
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UseMCID.OpInfo[UseMOIdx].isLookupPtrRegClass()) {
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// The entire loop body is within the current scheduling region
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// and the latency of this operation is assumed to be greater
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// than the latency of the loop.
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// TODO: Recursively mark data-edge predecessors as
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// isScheduleHigh too.
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SU->isScheduleHigh = true;
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}
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}
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LoopRegs.Deps.erase(I);
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}
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}
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// clear this register's use list
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if (Uses.contains(MO.getReg()))
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Uses[MO.getReg()].clear();
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if (!MO.isDead())
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DefList.clear();
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// Calls will not be reordered because of chain dependencies (see
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// below). Since call operands are dead, calls may continue to be added
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// to the DefList making dependence checking quadratic in the size of
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// the block. Instead, we leave only one call at the back of the
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// DefList.
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if (SU->isCall) {
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while (!DefList.empty() && DefList.back()->isCall)
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DefList.pop_back();
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}
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// Defs are pushed in the order they are visited and never reordered.
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DefList.push_back(SU);
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}
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}
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/// addVRegDefDeps - Add register output and data dependencies from this SUnit
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/// to instructions that occur later in the same scheduling region if they read
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/// from or write to the virtual register defined at OperIdx.
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///
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/// TODO: Hoist loop induction variable increments. This has to be
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/// reevaluated. Generally, IV scheduling should be done before coalescing.
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void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
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const MachineInstr *MI = SU->getInstr();
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unsigned Reg = MI->getOperand(OperIdx).getReg();
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// SSA defs do not have output/anti dependencies.
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// The current operand is a def, so we have at least one.
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//
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// FIXME: This optimization is disabled pending PR13112.
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//if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end())
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// return;
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// Add output dependence to the next nearest def of this vreg.
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//
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// Unless this definition is dead, the output dependence should be
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// transitively redundant with antidependencies from this definition's
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// uses. We're conservative for now until we have a way to guarantee the uses
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// are not eliminated sometime during scheduling. The output dependence edge
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// is also useful if output latency exceeds def-use latency.
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VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg);
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if (DefI == VRegDefs.end())
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VRegDefs.insert(VReg2SUnit(Reg, SU));
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else {
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SUnit *DefSU = DefI->SU;
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if (DefSU != SU && DefSU != &ExitSU) {
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unsigned OutLatency = TII->getOutputLatency(InstrItins, MI, OperIdx,
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DefSU->getInstr());
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DefSU->addPred(SDep(SU, SDep::Output, OutLatency, Reg));
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}
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DefI->SU = SU;
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}
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}
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/// addVRegUseDeps - Add a register data dependency if the instruction that
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/// defines the virtual register used at OperIdx is mapped to an SUnit. Add a
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/// register antidependency from this SUnit to instructions that occur later in
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/// the same scheduling region if they write the virtual register.
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///
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/// TODO: Handle ExitSU "uses" properly.
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void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
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MachineInstr *MI = SU->getInstr();
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unsigned Reg = MI->getOperand(OperIdx).getReg();
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// Lookup this operand's reaching definition.
|
|
assert(LIS && "vreg dependencies requires LiveIntervals");
|
|
LiveRangeQuery LRQ(LIS->getInterval(Reg), LIS->getInstructionIndex(MI));
|
|
VNInfo *VNI = LRQ.valueIn();
|
|
|
|
// VNI will be valid because MachineOperand::readsReg() is checked by caller.
|
|
assert(VNI && "No value to read by operand");
|
|
MachineInstr *Def = LIS->getInstructionFromIndex(VNI->def);
|
|
// Phis and other noninstructions (after coalescing) have a NULL Def.
|
|
if (Def) {
|
|
SUnit *DefSU = getSUnit(Def);
|
|
if (DefSU) {
|
|
// The reaching Def lives within this scheduling region.
|
|
// Create a data dependence.
|
|
//
|
|
// TODO: Handle "special" address latencies cleanly.
|
|
SDep dep(DefSU, SDep::Data, DefSU->Latency, Reg);
|
|
if (!UnitLatencies) {
|
|
// Adjust the dependence latency using operand def/use information, then
|
|
// allow the target to perform its own adjustments.
|
|
unsigned Latency = computeOperandLatency(DefSU, SU, const_cast<SDep &>(dep));
|
|
dep.setLatency(Latency);
|
|
|
|
const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
|
|
ST.adjustSchedDependency(DefSU, SU, const_cast<SDep &>(dep));
|
|
}
|
|
SU->addPred(dep);
|
|
}
|
|
}
|
|
|
|
// Add antidependence to the following def of the vreg it uses.
|
|
VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg);
|
|
if (DefI != VRegDefs.end() && DefI->SU != SU)
|
|
DefI->SU->addPred(SDep(SU, SDep::Anti, 0, Reg));
|
|
}
|
|
|
|
/// Return true if MI is an instruction we are unable to reason about
|
|
/// (like a call or something with unmodeled side effects).
|
|
static inline bool isGlobalMemoryObject(AliasAnalysis *AA, MachineInstr *MI) {
|
|
if (MI->isCall() || MI->hasUnmodeledSideEffects() ||
|
|
(MI->hasVolatileMemoryRef() &&
|
|
(!MI->mayLoad() || !MI->isInvariantLoad(AA))))
|
|
return true;
|
|
return false;
|
|
}
|
|
|
|
// This MI might have either incomplete info, or known to be unsafe
|
|
// to deal with (i.e. volatile object).
|
|
static inline bool isUnsafeMemoryObject(MachineInstr *MI,
|
|
const MachineFrameInfo *MFI) {
|
|
if (!MI || MI->memoperands_empty())
|
|
return true;
|
|
// We purposefully do no check for hasOneMemOperand() here
|
|
// in hope to trigger an assert downstream in order to
|
|
// finish implementation.
|
|
if ((*MI->memoperands_begin())->isVolatile() ||
|
|
MI->hasUnmodeledSideEffects())
|
|
return true;
|
|
|
|
const Value *V = (*MI->memoperands_begin())->getValue();
|
|
if (!V)
|
|
return true;
|
|
|
|
V = getUnderlyingObject(V);
|
|
if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
|
|
// Similarly to getUnderlyingObjectForInstr:
|
|
// For now, ignore PseudoSourceValues which may alias LLVM IR values
|
|
// because the code that uses this function has no way to cope with
|
|
// such aliases.
|
|
if (PSV->isAliased(MFI))
|
|
return true;
|
|
}
|
|
// Does this pointer refer to a distinct and identifiable object?
|
|
if (!isIdentifiedObject(V))
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
/// This returns true if the two MIs need a chain edge betwee them.
|
|
/// If these are not even memory operations, we still may need
|
|
/// chain deps between them. The question really is - could
|
|
/// these two MIs be reordered during scheduling from memory dependency
|
|
/// point of view.
|
|
static bool MIsNeedChainEdge(AliasAnalysis *AA, const MachineFrameInfo *MFI,
|
|
MachineInstr *MIa,
|
|
MachineInstr *MIb) {
|
|
// Cover a trivial case - no edge is need to itself.
|
|
if (MIa == MIb)
|
|
return false;
|
|
|
|
if (isUnsafeMemoryObject(MIa, MFI) || isUnsafeMemoryObject(MIb, MFI))
|
|
return true;
|
|
|
|
// If we are dealing with two "normal" loads, we do not need an edge
|
|
// between them - they could be reordered.
|
|
if (!MIa->mayStore() && !MIb->mayStore())
|
|
return false;
|
|
|
|
// To this point analysis is generic. From here on we do need AA.
|
|
if (!AA)
|
|
return true;
|
|
|
|
MachineMemOperand *MMOa = *MIa->memoperands_begin();
|
|
MachineMemOperand *MMOb = *MIb->memoperands_begin();
|
|
|
|
// FIXME: Need to handle multiple memory operands to support all targets.
|
|
if (!MIa->hasOneMemOperand() || !MIb->hasOneMemOperand())
|
|
llvm_unreachable("Multiple memory operands.");
|
|
|
|
// The following interface to AA is fashioned after DAGCombiner::isAlias
|
|
// and operates with MachineMemOperand offset with some important
|
|
// assumptions:
|
|
// - LLVM fundamentally assumes flat address spaces.
|
|
// - MachineOperand offset can *only* result from legalization and
|
|
// cannot affect queries other than the trivial case of overlap
|
|
// checking.
|
|
// - These offsets never wrap and never step outside
|
|
// of allocated objects.
|
|
// - There should never be any negative offsets here.
|
|
//
|
|
// FIXME: Modify API to hide this math from "user"
|
|
// FIXME: Even before we go to AA we can reason locally about some
|
|
// memory objects. It can save compile time, and possibly catch some
|
|
// corner cases not currently covered.
|
|
|
|
assert ((MMOa->getOffset() >= 0) && "Negative MachineMemOperand offset");
|
|
assert ((MMOb->getOffset() >= 0) && "Negative MachineMemOperand offset");
|
|
|
|
int64_t MinOffset = std::min(MMOa->getOffset(), MMOb->getOffset());
|
|
int64_t Overlapa = MMOa->getSize() + MMOa->getOffset() - MinOffset;
|
|
int64_t Overlapb = MMOb->getSize() + MMOb->getOffset() - MinOffset;
|
|
|
|
AliasAnalysis::AliasResult AAResult = AA->alias(
|
|
AliasAnalysis::Location(MMOa->getValue(), Overlapa,
|
|
MMOa->getTBAAInfo()),
|
|
AliasAnalysis::Location(MMOb->getValue(), Overlapb,
|
|
MMOb->getTBAAInfo()));
|
|
|
|
return (AAResult != AliasAnalysis::NoAlias);
|
|
}
|
|
|
|
/// This recursive function iterates over chain deps of SUb looking for
|
|
/// "latest" node that needs a chain edge to SUa.
|
|
static unsigned
|
|
iterateChainSucc(AliasAnalysis *AA, const MachineFrameInfo *MFI,
|
|
SUnit *SUa, SUnit *SUb, SUnit *ExitSU, unsigned *Depth,
|
|
SmallPtrSet<const SUnit*, 16> &Visited) {
|
|
if (!SUa || !SUb || SUb == ExitSU)
|
|
return *Depth;
|
|
|
|
// Remember visited nodes.
|
|
if (!Visited.insert(SUb))
|
|
return *Depth;
|
|
// If there is _some_ dependency already in place, do not
|
|
// descend any further.
|
|
// TODO: Need to make sure that if that dependency got eliminated or ignored
|
|
// for any reason in the future, we would not violate DAG topology.
|
|
// Currently it does not happen, but makes an implicit assumption about
|
|
// future implementation.
|
|
//
|
|
// Independently, if we encounter node that is some sort of global
|
|
// object (like a call) we already have full set of dependencies to it
|
|
// and we can stop descending.
|
|
if (SUa->isSucc(SUb) ||
|
|
isGlobalMemoryObject(AA, SUb->getInstr()))
|
|
return *Depth;
|
|
|
|
// If we do need an edge, or we have exceeded depth budget,
|
|
// add that edge to the predecessors chain of SUb,
|
|
// and stop descending.
|
|
if (*Depth > 200 ||
|
|
MIsNeedChainEdge(AA, MFI, SUa->getInstr(), SUb->getInstr())) {
|
|
SUb->addPred(SDep(SUa, SDep::Order, /*Latency=*/0, /*Reg=*/0,
|
|
/*isNormalMemory=*/true));
|
|
return *Depth;
|
|
}
|
|
// Track current depth.
|
|
(*Depth)++;
|
|
// Iterate over chain dependencies only.
|
|
for (SUnit::const_succ_iterator I = SUb->Succs.begin(), E = SUb->Succs.end();
|
|
I != E; ++I)
|
|
if (I->isCtrl())
|
|
iterateChainSucc (AA, MFI, SUa, I->getSUnit(), ExitSU, Depth, Visited);
|
|
return *Depth;
|
|
}
|
|
|
|
/// This function assumes that "downward" from SU there exist
|
|
/// tail/leaf of already constructed DAG. It iterates downward and
|
|
/// checks whether SU can be aliasing any node dominated
|
|
/// by it.
|
|
static void adjustChainDeps(AliasAnalysis *AA, const MachineFrameInfo *MFI,
|
|
SUnit *SU, SUnit *ExitSU, std::set<SUnit *> &CheckList,
|
|
unsigned LatencyToLoad) {
|
|
if (!SU)
|
|
return;
|
|
|
|
SmallPtrSet<const SUnit*, 16> Visited;
|
|
unsigned Depth = 0;
|
|
|
|
for (std::set<SUnit *>::iterator I = CheckList.begin(), IE = CheckList.end();
|
|
I != IE; ++I) {
|
|
if (SU == *I)
|
|
continue;
|
|
if (MIsNeedChainEdge(AA, MFI, SU->getInstr(), (*I)->getInstr())) {
|
|
unsigned Latency = ((*I)->getInstr()->mayLoad()) ? LatencyToLoad : 0;
|
|
(*I)->addPred(SDep(SU, SDep::Order, Latency, /*Reg=*/0,
|
|
/*isNormalMemory=*/true));
|
|
}
|
|
// Now go through all the chain successors and iterate from them.
|
|
// Keep track of visited nodes.
|
|
for (SUnit::const_succ_iterator J = (*I)->Succs.begin(),
|
|
JE = (*I)->Succs.end(); J != JE; ++J)
|
|
if (J->isCtrl())
|
|
iterateChainSucc (AA, MFI, SU, J->getSUnit(),
|
|
ExitSU, &Depth, Visited);
|
|
}
|
|
}
|
|
|
|
/// Check whether two objects need a chain edge, if so, add it
|
|
/// otherwise remember the rejected SU.
|
|
static inline
|
|
void addChainDependency (AliasAnalysis *AA, const MachineFrameInfo *MFI,
|
|
SUnit *SUa, SUnit *SUb,
|
|
std::set<SUnit *> &RejectList,
|
|
unsigned TrueMemOrderLatency = 0,
|
|
bool isNormalMemory = false) {
|
|
// If this is a false dependency,
|
|
// do not add the edge, but rememeber the rejected node.
|
|
if (!EnableAASchedMI ||
|
|
MIsNeedChainEdge(AA, MFI, SUa->getInstr(), SUb->getInstr()))
|
|
SUb->addPred(SDep(SUa, SDep::Order, TrueMemOrderLatency, /*Reg=*/0,
|
|
isNormalMemory));
|
|
else {
|
|
// Duplicate entries should be ignored.
|
|
RejectList.insert(SUb);
|
|
DEBUG(dbgs() << "\tReject chain dep between SU("
|
|
<< SUa->NodeNum << ") and SU("
|
|
<< SUb->NodeNum << ")\n");
|
|
}
|
|
}
|
|
|
|
/// Create an SUnit for each real instruction, numbered in top-down toplological
|
|
/// order. The instruction order A < B, implies that no edge exists from B to A.
|
|
///
|
|
/// Map each real instruction to its SUnit.
|
|
///
|
|
/// After initSUnits, the SUnits vector cannot be resized and the scheduler may
|
|
/// hang onto SUnit pointers. We may relax this in the future by using SUnit IDs
|
|
/// instead of pointers.
|
|
///
|
|
/// MachineScheduler relies on initSUnits numbering the nodes by their order in
|
|
/// the original instruction list.
|
|
void ScheduleDAGInstrs::initSUnits() {
|
|
// We'll be allocating one SUnit for each real instruction in the region,
|
|
// which is contained within a basic block.
|
|
SUnits.reserve(BB->size());
|
|
|
|
for (MachineBasicBlock::iterator I = RegionBegin; I != RegionEnd; ++I) {
|
|
MachineInstr *MI = I;
|
|
if (MI->isDebugValue())
|
|
continue;
|
|
|
|
SUnit *SU = newSUnit(MI);
|
|
MISUnitMap[MI] = SU;
|
|
|
|
SU->isCall = MI->isCall();
|
|
SU->isCommutable = MI->isCommutable();
|
|
|
|
// Assign the Latency field of SU using target-provided information.
|
|
if (UnitLatencies)
|
|
SU->Latency = 1;
|
|
else
|
|
computeLatency(SU);
|
|
}
|
|
}
|
|
|
|
/// If RegPressure is non null, compute register pressure as a side effect. The
|
|
/// DAG builder is an efficient place to do it because it already visits
|
|
/// operands.
|
|
void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
|
|
RegPressureTracker *RPTracker) {
|
|
// Create an SUnit for each real instruction.
|
|
initSUnits();
|
|
|
|
// We build scheduling units by walking a block's instruction list from bottom
|
|
// to top.
|
|
|
|
// Remember where a generic side-effecting instruction is as we procede.
|
|
SUnit *BarrierChain = 0, *AliasChain = 0;
|
|
|
|
// Memory references to specific known memory locations are tracked
|
|
// so that they can be given more precise dependencies. We track
|
|
// separately the known memory locations that may alias and those
|
|
// that are known not to alias
|
|
std::map<const Value *, SUnit *> AliasMemDefs, NonAliasMemDefs;
|
|
std::map<const Value *, std::vector<SUnit *> > AliasMemUses, NonAliasMemUses;
|
|
std::set<SUnit*> RejectMemNodes;
|
|
|
|
// Remove any stale debug info; sometimes BuildSchedGraph is called again
|
|
// without emitting the info from the previous call.
|
|
DbgValues.clear();
|
|
FirstDbgValue = NULL;
|
|
|
|
assert(Defs.empty() && Uses.empty() &&
|
|
"Only BuildGraph should update Defs/Uses");
|
|
Defs.setRegLimit(TRI->getNumRegs());
|
|
Uses.setRegLimit(TRI->getNumRegs());
|
|
|
|
assert(VRegDefs.empty() && "Only BuildSchedGraph may access VRegDefs");
|
|
// FIXME: Allow SparseSet to reserve space for the creation of virtual
|
|
// registers during scheduling. Don't artificially inflate the Universe
|
|
// because we want to assert that vregs are not created during DAG building.
|
|
VRegDefs.setUniverse(MRI.getNumVirtRegs());
|
|
|
|
// Model data dependencies between instructions being scheduled and the
|
|
// ExitSU.
|
|
addSchedBarrierDeps();
|
|
|
|
// Walk the list of instructions, from bottom moving up.
|
|
MachineInstr *PrevMI = NULL;
|
|
for (MachineBasicBlock::iterator MII = RegionEnd, MIE = RegionBegin;
|
|
MII != MIE; --MII) {
|
|
MachineInstr *MI = prior(MII);
|
|
if (MI && PrevMI) {
|
|
DbgValues.push_back(std::make_pair(PrevMI, MI));
|
|
PrevMI = NULL;
|
|
}
|
|
|
|
if (MI->isDebugValue()) {
|
|
PrevMI = MI;
|
|
continue;
|
|
}
|
|
if (RPTracker) {
|
|
RPTracker->recede();
|
|
assert(RPTracker->getPos() == prior(MII) && "RPTracker can't find MI");
|
|
}
|
|
|
|
assert((!MI->isTerminator() || CanHandleTerminators) && !MI->isLabel() &&
|
|
"Cannot schedule terminators or labels!");
|
|
|
|
SUnit *SU = MISUnitMap[MI];
|
|
assert(SU && "No SUnit mapped to this MI");
|
|
|
|
// Add register-based dependencies (data, anti, and output).
|
|
for (unsigned j = 0, n = MI->getNumOperands(); j != n; ++j) {
|
|
const MachineOperand &MO = MI->getOperand(j);
|
|
if (!MO.isReg()) continue;
|
|
unsigned Reg = MO.getReg();
|
|
if (Reg == 0) continue;
|
|
|
|
if (TRI->isPhysicalRegister(Reg))
|
|
addPhysRegDeps(SU, j);
|
|
else {
|
|
assert(!IsPostRA && "Virtual register encountered!");
|
|
if (MO.isDef())
|
|
addVRegDefDeps(SU, j);
|
|
else if (MO.readsReg()) // ignore undef operands
|
|
addVRegUseDeps(SU, j);
|
|
}
|
|
}
|
|
|
|
// Add chain dependencies.
|
|
// Chain dependencies used to enforce memory order should have
|
|
// latency of 0 (except for true dependency of Store followed by
|
|
// aliased Load... we estimate that with a single cycle of latency
|
|
// assuming the hardware will bypass)
|
|
// Note that isStoreToStackSlot and isLoadFromStackSLot are not usable
|
|
// after stack slots are lowered to actual addresses.
|
|
// TODO: Use an AliasAnalysis and do real alias-analysis queries, and
|
|
// produce more precise dependence information.
|
|
unsigned TrueMemOrderLatency = MI->mayStore() ? 1 : 0;
|
|
if (isGlobalMemoryObject(AA, MI)) {
|
|
// Be conservative with these and add dependencies on all memory
|
|
// references, even those that are known to not alias.
|
|
for (std::map<const Value *, SUnit *>::iterator I =
|
|
NonAliasMemDefs.begin(), E = NonAliasMemDefs.end(); I != E; ++I) {
|
|
I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
|
|
}
|
|
for (std::map<const Value *, std::vector<SUnit *> >::iterator I =
|
|
NonAliasMemUses.begin(), E = NonAliasMemUses.end(); I != E; ++I) {
|
|
for (unsigned i = 0, e = I->second.size(); i != e; ++i)
|
|
I->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
|
|
}
|
|
// Add SU to the barrier chain.
|
|
if (BarrierChain)
|
|
BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
|
|
BarrierChain = SU;
|
|
// This is a barrier event that acts as a pivotal node in the DAG,
|
|
// so it is safe to clear list of exposed nodes.
|
|
adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes,
|
|
TrueMemOrderLatency);
|
|
RejectMemNodes.clear();
|
|
NonAliasMemDefs.clear();
|
|
NonAliasMemUses.clear();
|
|
|
|
// fall-through
|
|
new_alias_chain:
|
|
// Chain all possibly aliasing memory references though SU.
|
|
if (AliasChain) {
|
|
unsigned ChainLatency = 0;
|
|
if (AliasChain->getInstr()->mayLoad())
|
|
ChainLatency = TrueMemOrderLatency;
|
|
addChainDependency(AA, MFI, SU, AliasChain, RejectMemNodes,
|
|
ChainLatency);
|
|
}
|
|
AliasChain = SU;
|
|
for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
|
|
addChainDependency(AA, MFI, SU, PendingLoads[k], RejectMemNodes,
|
|
TrueMemOrderLatency);
|
|
for (std::map<const Value *, SUnit *>::iterator I = AliasMemDefs.begin(),
|
|
E = AliasMemDefs.end(); I != E; ++I)
|
|
addChainDependency(AA, MFI, SU, I->second, RejectMemNodes);
|
|
for (std::map<const Value *, std::vector<SUnit *> >::iterator I =
|
|
AliasMemUses.begin(), E = AliasMemUses.end(); I != E; ++I) {
|
|
for (unsigned i = 0, e = I->second.size(); i != e; ++i)
|
|
addChainDependency(AA, MFI, SU, I->second[i], RejectMemNodes,
|
|
TrueMemOrderLatency);
|
|
}
|
|
adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes,
|
|
TrueMemOrderLatency);
|
|
PendingLoads.clear();
|
|
AliasMemDefs.clear();
|
|
AliasMemUses.clear();
|
|
} else if (MI->mayStore()) {
|
|
bool MayAlias = true;
|
|
if (const Value *V = getUnderlyingObjectForInstr(MI, MFI, MayAlias)) {
|
|
// A store to a specific PseudoSourceValue. Add precise dependencies.
|
|
// Record the def in MemDefs, first adding a dep if there is
|
|
// an existing def.
|
|
std::map<const Value *, SUnit *>::iterator I =
|
|
((MayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
|
|
std::map<const Value *, SUnit *>::iterator IE =
|
|
((MayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
|
|
if (I != IE) {
|
|
addChainDependency(AA, MFI, SU, I->second, RejectMemNodes,
|
|
0, true);
|
|
I->second = SU;
|
|
} else {
|
|
if (MayAlias)
|
|
AliasMemDefs[V] = SU;
|
|
else
|
|
NonAliasMemDefs[V] = SU;
|
|
}
|
|
// Handle the uses in MemUses, if there are any.
|
|
std::map<const Value *, std::vector<SUnit *> >::iterator J =
|
|
((MayAlias) ? AliasMemUses.find(V) : NonAliasMemUses.find(V));
|
|
std::map<const Value *, std::vector<SUnit *> >::iterator JE =
|
|
((MayAlias) ? AliasMemUses.end() : NonAliasMemUses.end());
|
|
if (J != JE) {
|
|
for (unsigned i = 0, e = J->second.size(); i != e; ++i)
|
|
addChainDependency(AA, MFI, SU, J->second[i], RejectMemNodes,
|
|
TrueMemOrderLatency, true);
|
|
J->second.clear();
|
|
}
|
|
if (MayAlias) {
|
|
// Add dependencies from all the PendingLoads, i.e. loads
|
|
// with no underlying object.
|
|
for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
|
|
addChainDependency(AA, MFI, SU, PendingLoads[k], RejectMemNodes,
|
|
TrueMemOrderLatency);
|
|
// Add dependence on alias chain, if needed.
|
|
if (AliasChain)
|
|
addChainDependency(AA, MFI, SU, AliasChain, RejectMemNodes);
|
|
// But we also should check dependent instructions for the
|
|
// SU in question.
|
|
adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes,
|
|
TrueMemOrderLatency);
|
|
}
|
|
// Add dependence on barrier chain, if needed.
|
|
// There is no point to check aliasing on barrier event. Even if
|
|
// SU and barrier _could_ be reordered, they should not. In addition,
|
|
// we have lost all RejectMemNodes below barrier.
|
|
if (BarrierChain)
|
|
BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
|
|
} else {
|
|
// Treat all other stores conservatively.
|
|
goto new_alias_chain;
|
|
}
|
|
|
|
if (!ExitSU.isPred(SU))
|
|
// Push store's up a bit to avoid them getting in between cmp
|
|
// and branches.
|
|
ExitSU.addPred(SDep(SU, SDep::Order, 0,
|
|
/*Reg=*/0, /*isNormalMemory=*/false,
|
|
/*isMustAlias=*/false,
|
|
/*isArtificial=*/true));
|
|
} else if (MI->mayLoad()) {
|
|
bool MayAlias = true;
|
|
if (MI->isInvariantLoad(AA)) {
|
|
// Invariant load, no chain dependencies needed!
|
|
} else {
|
|
if (const Value *V =
|
|
getUnderlyingObjectForInstr(MI, MFI, MayAlias)) {
|
|
// A load from a specific PseudoSourceValue. Add precise dependencies.
|
|
std::map<const Value *, SUnit *>::iterator I =
|
|
((MayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
|
|
std::map<const Value *, SUnit *>::iterator IE =
|
|
((MayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
|
|
if (I != IE)
|
|
addChainDependency(AA, MFI, SU, I->second, RejectMemNodes, 0, true);
|
|
if (MayAlias)
|
|
AliasMemUses[V].push_back(SU);
|
|
else
|
|
NonAliasMemUses[V].push_back(SU);
|
|
} else {
|
|
// A load with no underlying object. Depend on all
|
|
// potentially aliasing stores.
|
|
for (std::map<const Value *, SUnit *>::iterator I =
|
|
AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I)
|
|
addChainDependency(AA, MFI, SU, I->second, RejectMemNodes);
|
|
|
|
PendingLoads.push_back(SU);
|
|
MayAlias = true;
|
|
}
|
|
if (MayAlias)
|
|
adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes, /*Latency=*/0);
|
|
// Add dependencies on alias and barrier chains, if needed.
|
|
if (MayAlias && AliasChain)
|
|
addChainDependency(AA, MFI, SU, AliasChain, RejectMemNodes);
|
|
if (BarrierChain)
|
|
BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
|
|
}
|
|
}
|
|
}
|
|
if (PrevMI)
|
|
FirstDbgValue = PrevMI;
|
|
|
|
Defs.clear();
|
|
Uses.clear();
|
|
VRegDefs.clear();
|
|
PendingLoads.clear();
|
|
}
|
|
|
|
void ScheduleDAGInstrs::computeLatency(SUnit *SU) {
|
|
// Compute the latency for the node. We only provide a default for missing
|
|
// itineraries. Empty itineraries still have latency properties.
|
|
if (!InstrItins) {
|
|
SU->Latency = 1;
|
|
|
|
// Simplistic target-independent heuristic: assume that loads take
|
|
// extra time.
|
|
if (SU->getInstr()->mayLoad())
|
|
SU->Latency += 2;
|
|
} else {
|
|
SU->Latency = TII->getInstrLatency(InstrItins, SU->getInstr());
|
|
}
|
|
}
|
|
|
|
unsigned ScheduleDAGInstrs::computeOperandLatency(SUnit *Def, SUnit *Use,
|
|
const SDep& dep,
|
|
bool FindMin) const {
|
|
// For a data dependency with a known register...
|
|
if ((dep.getKind() != SDep::Data) || (dep.getReg() == 0))
|
|
return 1;
|
|
|
|
return TII->computeOperandLatency(InstrItins, TRI, Def->getInstr(),
|
|
Use->getInstr(), dep.getReg(), FindMin);
|
|
}
|
|
|
|
void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
|
|
SU->getInstr()->dump();
|
|
}
|
|
|
|
std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
|
|
std::string s;
|
|
raw_string_ostream oss(s);
|
|
if (SU == &EntrySU)
|
|
oss << "<entry>";
|
|
else if (SU == &ExitSU)
|
|
oss << "<exit>";
|
|
else
|
|
SU->getInstr()->print(oss);
|
|
return oss.str();
|
|
}
|
|
|
|
/// Return the basic block label. It is not necessarilly unique because a block
|
|
/// contains multiple scheduling regions. But it is fine for visualization.
|
|
std::string ScheduleDAGInstrs::getDAGName() const {
|
|
return "dag." + BB->getFullName();
|
|
}
|