Chad Rosier e5e674ba11 [fast-isel] Fallback to SelectionDAG isel if we require strict alignment for ... non-aligned i32 loads/stores. rdar://12304911 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164381 91177308-0d34-0410-b5e6-96231b3b80d8		2012-09-21 16:58:35 +00:00
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ARM	[fast-isel] Fallback to SelectionDAG isel if we require strict alignment for	2012-09-21 16:58:35 +00:00
CellSPU
CPP
Generic
Hexagon	LLVM Bug Fix 13709: Remove needless lsr(Rp, #32) instruction access the	2012-09-05 16:01:40 +00:00
MBlaze
Mips	Handled unaligned load/stores properly in Mips16	2012-09-15 01:02:03 +00:00
MSP430
NVPTX
PowerPC	Specify cpu to get the correct instruction ordering. Remove XFAIL.	2012-09-20 14:59:42 +00:00
SPARC	Move load_to_switch.ll to test/CodeGen/SPARC/	2012-09-19 09:25:03 +00:00
Thumb	Fix Thumb2 fixup kind in the integrated-as.	2012-09-01 15:06:36 +00:00
Thumb2	Use vld1 / vst2 for unaligned v2f64 load / store. e.g. Use vld1.16 for 2-byte	2012-09-18 01:42:45 +00:00
X86	llvm/test/CodeGen/X86/pr5145.ll: Tweak expressions to match for darwin target.	2012-09-21 05:19:19 +00:00
XCore