mirror of
https://github.com/c64scene-ar/llvm-6502.git
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02c2ecf9f1
That can usually be lowered efficiently and is common in sandybridge code. It would be nice to do this in DAGCombiner but we can't insert arbitrary BUILD_VECTORs this late. Fixes PR15462. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176634 91177308-0d34-0410-b5e6-96231b3b80d8
148 lines
4.3 KiB
LLVM
148 lines
4.3 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
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;;; Shift left
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; CHECK: vpslld
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; CHECK: vpslld
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define <8 x i32> @vshift00(<8 x i32> %a) nounwind readnone {
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%s = shl <8 x i32> %a, <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32
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2>
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ret <8 x i32> %s
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}
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; CHECK: vpsllw
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; CHECK: vpsllw
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define <16 x i16> @vshift01(<16 x i16> %a) nounwind readnone {
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%s = shl <16 x i16> %a, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
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ret <16 x i16> %s
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}
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; CHECK: vpsllq
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; CHECK: vpsllq
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define <4 x i64> @vshift02(<4 x i64> %a) nounwind readnone {
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%s = shl <4 x i64> %a, <i64 2, i64 2, i64 2, i64 2>
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ret <4 x i64> %s
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}
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;;; Logical Shift right
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; CHECK: vpsrld
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; CHECK: vpsrld
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define <8 x i32> @vshift03(<8 x i32> %a) nounwind readnone {
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%s = lshr <8 x i32> %a, <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32
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2>
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ret <8 x i32> %s
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}
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; CHECK: vpsrlw
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; CHECK: vpsrlw
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define <16 x i16> @vshift04(<16 x i16> %a) nounwind readnone {
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%s = lshr <16 x i16> %a, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
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ret <16 x i16> %s
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}
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; CHECK: vpsrlq
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; CHECK: vpsrlq
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define <4 x i64> @vshift05(<4 x i64> %a) nounwind readnone {
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%s = lshr <4 x i64> %a, <i64 2, i64 2, i64 2, i64 2>
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ret <4 x i64> %s
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}
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;;; Arithmetic Shift right
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; CHECK: vpsrad
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; CHECK: vpsrad
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define <8 x i32> @vshift06(<8 x i32> %a) nounwind readnone {
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%s = ashr <8 x i32> %a, <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32
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2>
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ret <8 x i32> %s
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}
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; CHECK: vpsraw
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; CHECK: vpsraw
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define <16 x i16> @vshift07(<16 x i16> %a) nounwind readnone {
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%s = ashr <16 x i16> %a, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
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ret <16 x i16> %s
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}
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; CHECK: vpsrlw
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; CHECK: pand
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; CHECK: pxor
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; CHECK: psubb
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; CHECK: vpsrlw
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; CHECK: pand
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; CHECK: pxor
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; CHECK: psubb
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define <32 x i8> @vshift09(<32 x i8> %a) nounwind readnone {
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%s = ashr <32 x i8> %a, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
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ret <32 x i8> %s
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}
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; CHECK: pxor
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; CHECK: pcmpgtb
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; CHECK: pcmpgtb
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define <32 x i8> @vshift10(<32 x i8> %a) nounwind readnone {
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%s = ashr <32 x i8> %a, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
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ret <32 x i8> %s
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}
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; CHECK: vpsrlw
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; CHECK: pand
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; CHECK: vpsrlw
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; CHECK: pand
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define <32 x i8> @vshift11(<32 x i8> %a) nounwind readnone {
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%s = lshr <32 x i8> %a, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
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ret <32 x i8> %s
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}
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; CHECK: vpsllw
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; CHECK: pand
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; CHECK: vpsllw
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; CHECK: pand
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define <32 x i8> @vshift12(<32 x i8> %a) nounwind readnone {
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%s = shl <32 x i8> %a, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
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ret <32 x i8> %s
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}
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;;; Support variable shifts
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; CHECK: _vshift08
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; CHECK: vextractf128 $1
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; CHECK: vpslld $23
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; CHECK: vpslld $23
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define <8 x i32> @vshift08(<8 x i32> %a) nounwind {
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%bitop = shl <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, %a
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ret <8 x i32> %bitop
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}
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; PR15141
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; CHECK: _vshift13:
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; CHECK-NOT: vpsll
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; CHECK: vcvttps2dq
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; CHECK-NEXT: vpmulld
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define <4 x i32> @vshift13(<4 x i32> %in) {
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%T = shl <4 x i32> %in, <i32 0, i32 1, i32 2, i32 4>
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ret <4 x i32> %T
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}
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;;; Uses shifts for sign extension
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; CHECK: _sext_v16i16
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; CHECK: vpsllw
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; CHECK: vpsraw
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; CHECK: vpsllw
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; CHECK: vpsraw
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; CHECK: vinsertf128
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define <16 x i16> @sext_v16i16(<16 x i16> %a) nounwind {
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%b = trunc <16 x i16> %a to <16 x i8>
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%c = sext <16 x i8> %b to <16 x i16>
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ret <16 x i16> %c
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}
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; CHECK: _sext_v8i32
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; CHECK: vpslld
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; CHECK: vpsrad
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; CHECK: vpslld
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; CHECK: vpsrad
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; CHECK: vinsertf128
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define <8 x i32> @sext_v8i32(<8 x i32> %a) nounwind {
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%b = trunc <8 x i32> %a to <8 x i16>
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%c = sext <8 x i16> %b to <8 x i32>
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ret <8 x i32> %c
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}
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