mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
15983b80a0
Instead of having a bunch of separate MOV8r0, MOV16r0, ... pseudo-instructions, it's better to use a single MOV32r0 (which will expand to "xorl %reg, %reg") and obtain other sizes with EXTRACT_SUBREG and SUBREG_TO_REG. The encoding is smaller and partial register updates can sometimes be avoided. Until recently, this sequence was a barrier to rematerialization though. That should now be fixed so it's an appropriate time to make the change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182928 91177308-0d34-0410-b5e6-96231b3b80d8
42 lines
846 B
LLVM
42 lines
846 B
LLVM
; RUN: llc -mtriple=x86_64-none-linux -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
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define i64 @test_sdiv64(i64 %dividend, i64 %divisor) nounwind {
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entry:
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%result = sdiv i64 %dividend, %divisor
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ret i64 %result
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}
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; CHECK: test_sdiv64:
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; CHECK: cqto
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; CHECK: idivq
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define i64 @test_srem64(i64 %dividend, i64 %divisor) nounwind {
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entry:
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%result = srem i64 %dividend, %divisor
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ret i64 %result
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}
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; CHECK: test_srem64:
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; CHECK: cqto
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; CHECK: idivq
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define i64 @test_udiv64(i64 %dividend, i64 %divisor) nounwind {
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entry:
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%result = udiv i64 %dividend, %divisor
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ret i64 %result
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}
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; CHECK: test_udiv64:
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; CHECK: xorl
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; CHECK: divq
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define i64 @test_urem64(i64 %dividend, i64 %divisor) nounwind {
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entry:
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%result = urem i64 %dividend, %divisor
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ret i64 %result
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}
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; CHECK: test_urem64:
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; CHECK: xorl
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; CHECK: divq
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