Chad Rosier 73f468218f [AArch64] Refactor the NEON scalar floating-point reciprocal step and ... floating-point reciprocal square root step LLVM AArch64 intrinsics to use f32/f64 types, rather than their vector equivalents. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197067 91177308-0d34-0410-b5e6-96231b3b80d8		2013-12-11 21:03:43 +00:00
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AArch64	[AArch64] Refactor the NEON scalar floating-point reciprocal step and	2013-12-11 21:03:43 +00:00
ARM	ARM: constrain register-class in fast-isel	2013-12-11 16:04:57 +00:00
CPP
Generic
Hexagon
Inputs
Mips	Distinguish and choose 16 or 32 bit forms of save/restore for Mips16.	2013-12-11 03:32:44 +00:00
MSP430
NVPTX	[NVPTX] Fix off-by-one error when creating the VT list for an SDNode	2013-12-05 12:58:00 +00:00
PowerPC	on darwin<10, fallback to .weak_definition (PPC,X86)	2013-12-10 21:37:41 +00:00
R600	R600/SI: Add i64 cmp tests	2013-12-10 21:11:55 +00:00
SPARC	[SPARCV9]: Adjust the resultant pointer of DYNAMIC_STACKALLOC with the stack BIAS on sparcV9.	2013-12-09 05:13:25 +00:00
SystemZ	[SystemZ] Optimize fcmp X, 0 in cases where X is also negated	2013-12-11 11:45:08 +00:00
Thumb	Use FileCheck and expand the test a bit.	2013-11-27 19:22:14 +00:00
Thumb2	Add support for parsing ARM symbol variants on ELF targets	2013-12-04 22:43:20 +00:00
X86	AVX-512: Removed "z" suffix from AVX-512 instructions, since it is incompatible with GCC.	2013-12-11 14:31:04 +00:00
XCore	XCore target: Make handling of large frames not dependent upon an FP.	2013-12-02 11:05:28 +00:00