Hal Finkel 8faeecead0 Revert "r232027 - Add infrastructure for support of multiple memory constraints" ... This (r232027) has caused PR22883; so it seems those bits might be used by something else after all. Reverting until we can figure out what else to do. Original commit message: The operand flag word for ISD::INLINEASM nodes now contains a 15-bit memory constraint ID when the operand kind is Kind_Mem. This constraint ID is a numeric equivalent to the constraint code string and is converted with a target specific hook in TargetLowering. This patch maps all memory constraints to InlineAsm::Constraint_m so there is no functional change at this point. It just proves that using these previously unused bits in the encoding of the flag word doesn't break anything. The next patch will make each target preserve the current mapping of everything to Constraint_m for itself while changing the target independent implementation of the hook to return Constraint_Unknown appropriately. Each target will then be adapted in separate patches to use appropriate Constraint_* values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232093 91177308-0d34-0410-b5e6-96231b3b80d8		2015-03-12 20:09:39 +00:00
..
CostTable.h
Target.td	Reverted 230471 - gather scatter handling in table gen.	2015-03-01 08:23:41 +00:00
TargetCallingConv.h
TargetCallingConv.td
TargetFrameLowering.h
TargetInstrInfo.h	ArrayRefize memory operand folding. NFC.	2015-02-28 12:04:00 +00:00
TargetIntrinsicInfo.h
TargetItinerary.td
TargetLowering.h	Revert "r232027 - Add infrastructure for support of multiple memory constraints"	2015-03-12 20:09:39 +00:00
TargetLoweringObjectFile.h	[AsmPrinter][TLOF] 32-bit MachO support for replacing GOT equivalents	2015-03-06 13:49:05 +00:00
TargetMachine.h	Move the DataLayout to the generic TargetMachine, making it mandatory.	2015-03-12 00:07:24 +00:00
TargetOpcodes.h
TargetOptions.h
TargetRegisterInfo.h	Have getCallPreservedMask and getThisCallPreservedMask take a	2015-03-11 22:42:13 +00:00
TargetSchedule.td
TargetSelectionDAG.td	[TableGen] Add support constraining a vector type in a pattern to have a specific element type and for constraining a vector type to have the same number of elements as another vector type. This is useful for AVX512 mask operations so we relate the mask type to the type of the other arguments.	2015-03-05 07:11:34 +00:00
TargetSelectionDAGInfo.h
TargetSubtargetInfo.h	Remove useMachineScheduler and replace it with subtarget options	2015-03-11 22:56:10 +00:00