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Revert "r232027 - Add infrastructure for support of multiple memory constraints"

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This (r232027) has caused PR22883; so it seems those bits might be used by
something else after all. Reverting until we can figure out what else to do.

Original commit message:

The operand flag word for ISD::INLINEASM nodes now contains a 15-bit
memory constraint ID when the operand kind is Kind_Mem. This constraint
ID is a numeric equivalent to the constraint code string and is converted
with a target specific hook in TargetLowering.

This patch maps all memory constraints to InlineAsm::Constraint_m so there
is no functional change at this point. It just proves that using these
previously unused bits in the encoding of the flag word doesn't break anything.

The next patch will make each target preserve the current mapping of
everything to Constraint_m for itself while changing the target independent
implementation of the hook to return Constraint_Unknown appropriately. Each
target will then be adapted in separate patches to use appropriate Constraint_*
values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232093 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2015-03-12 20:09:39 +00:00
parent fed84edb61
commit 8faeecead0
18 changed files with 44 additions and 107 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
include/llvm/CodeGen/SelectionDAGISel.h
View File

@ -80,12 +80,12 @@ public:
virtual SDNode *Select(SDNode *N) = 0;
/// SelectInlineAsmMemoryOperand - Select the specified address as a target
/// addressing mode, according to the specified constraint. If this does
/// addressing mode, according to the specified constraint code. If this does
/// not match or is not implemented, return true. The resultant operands
/// (which will appear in the machine instruction) should be added to the
/// OutOps vector.
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
unsigned ConstraintID,
char ConstraintCode,
std::vector<SDValue> &OutOps) {
return true;
}

38
include/llvm/IR/InlineAsm.h
View File

@ -189,19 +189,6 @@ public:
// These are helper methods for dealing with flags in the INLINEASM SDNode
// in the backend.
//
// The encoding of the flag word is currently:
// Bits 2-0 - A Kind_* value indicating the kind of the operand.
// Bits 15-3 - The number of SDNode operands associated with this inline
// assembly operand.
// If bits 2-0 are Kind_Mem:
// Bit 31 - 0
// Bit 30-16 - A Constraint_* value indicating the original constraint
// code.
// Else if bit 31 is set:
// Bit 30-16 - The operand number that this operand must match.
// Else if bit 31 is clear:
// Bit 30-16 - The register class ID to use for the operand.
enum : uint32_t {
// Fixed operands on an INLINEASM SDNode.
@ -233,17 +220,6 @@ public:
Kind_Imm = 5, // Immediate.
Kind_Mem = 6, // Memory operand, "m".
// Memory constraint codes.
// These could be tablegenerated but there's little need to do that since
// there's plenty of space in the encoding to support the union of all
// constraint codes for all targets.
Constraint_Unknown = 0,
Constraint_m,
Constraint_o, // Unused at the moment since Constraint_m is always used.
Constraint_v, // Unused at the moment since Constraint_m is always used.
Constraints_Max = Constraint_v,
Constraints_ShiftAmount = 16,
Flag_MatchingOperand = 0x80000000
};
@ -276,15 +252,6 @@ public:
return InputFlag | (RC << 16);
}
/// Augment an existing flag word returned by getFlagWord with the constraint
/// code for a memory constraint.
static unsigned getFlagWordForMem(unsigned InputFlag, unsigned Constraint) {
assert(Constraint <= 0x7fff && "Too large a memory constraint ID");
assert(Constraint <= Constraints_Max && "Unknown constraint ID");
assert((InputFlag & ~0xffff) == 0 && "High bits already contain data");
return InputFlag | (Constraint << Constraints_ShiftAmount);
}
static unsigned getKind(unsigned Flags) {
return Flags & 7;
}
@ -299,11 +266,6 @@ public:
return getKind(Flag) == Kind_Clobber;
}
static unsigned getMemoryConstraintID(unsigned Flag) {
assert(isMemKind(Flag));
return (Flag >> Constraints_ShiftAmount) & 0x7fff;
}
/// getNumOperandRegisters - Extract the number of registers field from the
/// inline asm operand flag.
static unsigned getNumOperandRegisters(unsigned Flag) {

7
include/llvm/Target/TargetLowering.h
View File

@ -2625,13 +2625,6 @@ public:
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
const std::string &Constraint, MVT VT) const;
virtual unsigned
getInlineAsmMemConstraint(const std::string &ConstraintCode) const {
// FIXME: This currently maps all constraints to the the same code.
// This will be corrected once all targets are updated.
return InlineAsm::Constraint_m;
}
/// Try to replace an X constraint, which matches anything, with another that
/// has more specific requirements based on the type of the corresponding
/// operand. This returns null if there is no replacement to make.

12
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -6595,14 +6595,8 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
// Memory output, or 'other' output (e.g. 'X' constraint).
assert(OpInfo.isIndirect && "Memory output must be indirect operand");
unsigned ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
assert(ConstraintID != InlineAsm::Constraint_Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM node to know about this output.
unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, MVT::i32));
AsmNodeOperands.push_back(OpInfo.CallOperand);
break;
@ -6746,14 +6740,8 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
"Memory operands expect pointer values");
unsigned ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
assert(ConstraintID != InlineAsm::Constraint_Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM node to know about this input.
unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, MVT::i32));
AsmNodeOperands.push_back(InOperandVal);
break;

4
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -1781,9 +1781,7 @@ SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
"Memory operand with multiple values?");
// Otherwise, this is a memory operand. Ask the target to select it.
std::vector<SDValue> SelOps;
if (SelectInlineAsmMemoryOperand(InOps[i+1],
InlineAsm::getMemoryConstraintID(Flags),
SelOps))
if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
report_fatal_error("Could not match memory address. Inline asm"
" failure!");

7
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
View File

@ -65,7 +65,7 @@ public:
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
bool SelectInlineAsmMemoryOperand(const SDValue &Op,
unsigned ConstraintID,
char ConstraintCode,
std::vector<SDValue> &OutOps) override;
SDNode *SelectMLAV64LaneV128(SDNode *N);
@ -211,9 +211,8 @@ static bool isOpcWithIntImmediate(const SDNode *N, unsigned Opc,
}
bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(
const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
assert(ConstraintID == InlineAsm::Constraint_m &&
"unexpected asm memory constraint");
const SDValue &Op, char ConstraintCode, std::vector<SDValue> &OutOps) {
assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
// Require the address to be in a register. That is safe for all AArch64
// variants and it is hard to do anything much smarter without knowing
// how the operand is used.

7
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -257,7 +257,7 @@ private:
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
std::vector<SDValue> &OutOps) override;
// Form pairs of consecutive R, S, D, or Q registers.
@ -3472,10 +3472,9 @@ SDNode *ARMDAGToDAGISel::SelectInlineAsm(SDNode *N){
bool ARMDAGToDAGISel::
SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
std::vector<SDValue> &OutOps) {
assert(ConstraintID == InlineAsm::Constraint_m &&
"unexpected asm memory constraint");
assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
// Require the address to be in a register. That is safe for all ARM
// variants and it is hard to do anything much smarter without knowing
// how the operand is used.

12
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
View File

@ -71,7 +71,7 @@ public:
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
bool SelectInlineAsmMemoryOperand(const SDValue &Op,
unsigned ConstraintID,
char ConstraintCode,
std::vector<SDValue> &OutOps) override;
SDNode *SelectLoad(SDNode *N);
SDNode *SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl);
@ -1103,16 +1103,16 @@ SDNode *HexagonDAGToDAGISel::Select(SDNode *N) {
bool HexagonDAGToDAGISel::
SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
std::vector<SDValue> &OutOps) {
SDValue Inp = Op, Res;
switch (ConstraintID) {
case InlineAsm::Constraint_o: // Offsetable.
case InlineAsm::Constraint_v: // Not offsetable.
switch (ConstraintCode) {
case 'o': // Offsetable.
case 'v': // Not offsetable.
default:
return true;
case InlineAsm::Constraint_m: // Memory.
case 'm': // Memory.
if (SelectAddrFI(Inp, Res))
OutOps.push_back(Res);
else

8
lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
View File

@ -104,7 +104,7 @@ namespace {
bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
std::vector<SDValue> &OutOps) override;
// Include the pieces autogenerated from the target description.
@ -280,12 +280,12 @@ bool MSP430DAGToDAGISel::SelectAddr(SDValue N,
}
bool MSP430DAGToDAGISel::
SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
std::vector<SDValue> &OutOps) {
SDValue Op0, Op1;
switch (ConstraintID) {
switch (ConstraintCode) {
default: return true;
case InlineAsm::Constraint_m: // memory
case 'm': // memory
if (!SelectAddr(Op, Op0, Op1))
return true;
break;

5
lib/Target/Mips/MipsISelDAGToDAG.cpp
View File

@ -230,10 +230,9 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
}
bool MipsDAGToDAGISel::
SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
std::vector<SDValue> &OutOps) {
assert(ConstraintID == InlineAsm::Constraint_m &&
"unexpected asm memory constraint");
assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
OutOps.push_back(Op);
return false;
}

2
lib/Target/Mips/MipsISelDAGToDAG.h
View File

@ -125,7 +125,7 @@ private:
virtual void processFunctionAfterISel(MachineFunction &MF) = 0;
bool SelectInlineAsmMemoryOperand(const SDValue &Op,
unsigned ConstraintID,
char ConstraintCode,
std::vector<SDValue> &OutOps) override;
};
}

6
lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
View File

@ -5044,12 +5044,12 @@ bool NVPTXDAGToDAGISel::ChkMemSDNodeAddressSpace(SDNode *N,
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
bool NVPTXDAGToDAGISel::SelectInlineAsmMemoryOperand(
const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
const SDValue &Op, char ConstraintCode, std::vector<SDValue> &OutOps) {
SDValue Op0, Op1;
switch (ConstraintID) {
switch (ConstraintCode) {
default:
return true;
case InlineAsm::Constraint_m: // memory
case 'm': // memory
if (SelectDirectAddr(Op, Op0)) {
OutOps.push_back(Op0);
OutOps.push_back(CurDAG->getTargetConstant(0, MVT::i32));

2
lib/Target/NVPTX/NVPTXISelDAGToDAG.h
View File

@ -48,7 +48,7 @@ public:
const NVPTXSubtarget *Subtarget;
bool SelectInlineAsmMemoryOperand(const SDValue &Op,
unsigned ConstraintID,
char ConstraintCode,
std::vector<SDValue> &OutOps) override;
private:
// Include the pieces autogenerated from the target description.

2
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -186,7 +186,7 @@ namespace {
/// register can be improved, but it is wrong to substitute Reg+Reg for
/// Reg in an asm, because the load or store opcode would have to change.
bool SelectInlineAsmMemoryOperand(const SDValue &Op,
unsigned ConstraintID,
char ConstraintCode,
std::vector<SDValue> &OutOps) override {
// We need to make sure that this one operand does not end up in r0
// (because we might end up lowering this as 0(%op)).

8
lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@ -50,7 +50,7 @@ public:
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
bool SelectInlineAsmMemoryOperand(const SDValue &Op,
unsigned ConstraintID,
char ConstraintCode,
std::vector<SDValue> &OutOps) override;
const char *getPassName() const override {
@ -195,12 +195,12 @@ SDNode *SparcDAGToDAGISel::Select(SDNode *N) {
/// inline asm expressions.
bool
SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
unsigned ConstraintID,
char ConstraintCode,
std::vector<SDValue> &OutOps) {
SDValue Op0, Op1;
switch (ConstraintID) {
switch (ConstraintCode) {
default: return true;
case InlineAsm::Constraint_m: // memory
case 'm': // memory
if (!SelectADDRrr(Op, Op0, Op1))
SelectADDRri(Op, Op0, Op1);
break;

7
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
View File

@ -328,7 +328,7 @@ public:
// Override SelectionDAGISel.
SDNode *Select(SDNode *Node) override;
bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
std::vector<SDValue> &OutOps) override;
// Include the pieces autogenerated from the target description.
@ -1129,10 +1129,9 @@ SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) {
bool SystemZDAGToDAGISel::
SelectInlineAsmMemoryOperand(const SDValue &Op,
unsigned ConstraintID,
char ConstraintCode,
std::vector<SDValue> &OutOps) {
assert(ConstraintID == InlineAsm::Constraint_m &&
"Unexpected constraint code");
assert(ConstraintCode == 'm' && "Unexpected constraint code");
// Accept addresses with short displacements, which are compatible
// with Q, R, S and T. But keep the index operand for future expansion.
SDValue Base, Disp, Index;

12
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -228,7 +228,7 @@ namespace {
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
bool SelectInlineAsmMemoryOperand(const SDValue &Op,
unsigned ConstraintID,
char ConstraintCode,
std::vector<SDValue> &OutOps) override;
void EmitSpecialCodeForMain();
@ -2814,14 +2814,14 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
}
bool X86DAGToDAGISel::
SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
std::vector<SDValue> &OutOps) {
SDValue Op0, Op1, Op2, Op3, Op4;
switch (ConstraintID) {
case InlineAsm::Constraint_o: // offsetable ??
case InlineAsm::Constraint_v: // not offsetable ??
switch (ConstraintCode) {
case 'o': // offsetable ??
case 'v': // not offsetable ??
default: return true;
case InlineAsm::Constraint_m: // memory
case 'm': // memory
if (!SelectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4))
return true;
break;

8
lib/Target/XCore/XCoreISelDAGToDAG.cpp
View File

@ -65,7 +65,7 @@ namespace {
// Complex Pattern Selectors.
bool SelectADDRspii(SDValue Addr, SDValue &Base, SDValue &Offset);
bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
std::vector<SDValue> &OutOps) override;
const char *getPassName() const override {
@ -108,12 +108,12 @@ bool XCoreDAGToDAGISel::SelectADDRspii(SDValue Addr, SDValue &Base,
}
bool XCoreDAGToDAGISel::
SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
std::vector<SDValue> &OutOps) {
SDValue Reg;
switch (ConstraintID) {
switch (ConstraintCode) {
default: return true;
case InlineAsm::Constraint_m: // Memory.
case 'm': // Memory.
switch (Op.getOpcode()) {
default: return true;
case XCoreISD::CPRelativeWrapper: