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https://github.com/c64scene-ar/llvm-6502.git
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7ea1ab5f41
support for the case where alignment<value size. These cases were silently miscompiled before this patch. Now they are overly verbose -especially storing is- and any front-end should still avoid misaligned memory accesses as much as possible. The bit juggling algorithm added here probably has some room for improvement still. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118889 91177308-0d34-0410-b5e6-96231b3b80d8
53 lines
1.4 KiB
LLVM
53 lines
1.4 KiB
LLVM
; RUN: llc < %s -march=cellspu | FileCheck %s
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; ModuleID = 'loads.bc'
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target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
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target triple = "spu"
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define <4 x float> @load_v4f32_1(<4 x float>* %a) nounwind readonly {
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entry:
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%tmp1 = load <4 x float>* %a
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ret <4 x float> %tmp1
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; CHECK: lqd $3, 0($3)
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}
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define <4 x float> @load_v4f32_2(<4 x float>* %a) nounwind readonly {
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entry:
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%arrayidx = getelementptr <4 x float>* %a, i32 1
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%tmp1 = load <4 x float>* %arrayidx
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ret <4 x float> %tmp1
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; CHECK: lqd $3, 16($3)
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}
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declare <4 x i32>* @getv4f32ptr()
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define <4 x i32> @func() {
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;CHECK: brasl
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; we need to have some instruction to move the result to safety.
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; which instruction (lr, stqd...) depends on the regalloc
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;CHECK: {{.*}}
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;CHECK: brasl
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%rv1 = call <4 x i32>* @getv4f32ptr()
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%rv2 = call <4 x i32>* @getv4f32ptr()
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%rv3 = load <4 x i32>* %rv1
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ret <4 x i32> %rv3
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}
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define <4 x float> @load_undef(){
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; CHECK: lqd $3, 0($3)
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%val = load <4 x float>* undef
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ret <4 x float> %val
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}
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;check that 'misaligned' loads that may span two memory chunks
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;have two loads. Don't check for the bitmanipulation, as that
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;might change with improved algorithms or scheduling
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define i32 @load_misaligned( i32* %ptr ){
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;CHECK: load_misaligned
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;CHECK: lqd
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;CHECK: lqd
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;CHECK: bi $lr
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%rv = load i32* %ptr, align 2
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ret i32 %rv
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}
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