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Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8
792 lines
33 KiB
C++
792 lines
33 KiB
C++
//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the target machine instructions to the code generator.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_TARGETINSTRINFO_H
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#define LLVM_TARGET_TARGETINSTRINFO_H
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/Support/DataTypes.h"
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#include <vector>
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#include <cassert>
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namespace llvm {
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class TargetRegisterClass;
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class LiveVariables;
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class CalleeSavedInfo;
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class SDNode;
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class SelectionDAG;
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template<class T> class SmallVectorImpl;
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//===----------------------------------------------------------------------===//
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// Machine Operand Flags and Description
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//===----------------------------------------------------------------------===//
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namespace TOI {
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// Operand constraints: only "tied_to" for now.
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enum OperandConstraint {
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TIED_TO = 0 // Must be allocated the same register as.
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};
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/// OperandFlags - These are flags set on operands, but should be considered
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/// private, all access should go through the TargetOperandInfo accessors.
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/// See the accessors for a description of what these are.
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enum OperandFlags {
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LookupPtrRegClass = 0,
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Predicate,
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OptionalDef
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};
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}
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/// TargetOperandInfo - This holds information about one operand of a machine
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/// instruction, indicating the register class for register operands, etc.
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///
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class TargetOperandInfo {
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public:
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/// RegClass - This specifies the register class enumeration of the operand
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/// if the operand is a register. If not, this contains 0.
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unsigned short RegClass;
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unsigned short Flags;
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/// Lower 16 bits are used to specify which constraints are set. The higher 16
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/// bits are used to specify the value of constraints (4 bits each).
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unsigned int Constraints;
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/// Currently no other information.
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/// isLookupPtrRegClass - Set if this operand is a pointer value and it
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/// requires a callback to look up its register class.
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bool isLookupPtrRegClass() const { return Flags&(1 <<TOI::LookupPtrRegClass);}
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/// isPredicate - Set if this is one of the operands that made up of
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/// the predicate operand that controls an isPredicable() instruction.
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bool isPredicate() const { return Flags & (1 << TOI::Predicate); }
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/// isOptionalDef - Set if this operand is a optional def.
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///
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bool isOptionalDef() const { return Flags & (1 << TOI::OptionalDef); }
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};
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//===----------------------------------------------------------------------===//
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// Machine Instruction Flags and Description
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//===----------------------------------------------------------------------===//
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/// TargetInstrDesc flags - These should be considered private to the
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/// implementation of the TargetInstrDesc class. Clients should use the
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/// predicate methods on TargetInstrDesc, not use these directly. These
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/// all correspond to bitfields in the TargetInstrDesc::Flags field.
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namespace TID {
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enum {
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Variadic = 0,
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HasOptionalDef,
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Return,
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Call,
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ImplicitDef,
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Barrier,
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Terminator,
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Branch,
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IndirectBranch,
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Predicable,
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NotDuplicable,
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DelaySlot,
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SimpleLoad,
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MayStore,
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NeverHasSideEffects,
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MayHaveSideEffects,
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Commutable,
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ConvertibleTo3Addr,
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UsesCustomDAGSchedInserter,
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Rematerializable
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};
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}
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/// TargetInstrDesc - Describe properties that are true of each
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/// instruction in the target description file. This captures information about
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/// side effects, register use and many other things. There is one instance of
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/// this struct for each target instruction class, and the MachineInstr class
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/// points to this struct directly to describe itself.
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class TargetInstrDesc {
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public:
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unsigned short Opcode; // The opcode number.
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unsigned short NumOperands; // Num of args (may be more if variable_ops)
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unsigned short NumDefs; // Num of args that are definitions.
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unsigned short SchedClass; // enum identifying instr sched class
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const char * Name; // Name of the instruction record in td file.
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unsigned Flags; // flags identifying machine instr class
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unsigned TSFlags; // Target Specific Flag values
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const unsigned *ImplicitUses; // Registers implicitly read by this instr
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const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
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const TargetOperandInfo *OpInfo; // 'NumOperands' entries about operands.
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/// getOperandConstraint - Returns the value of the specific constraint if
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/// it is set. Returns -1 if it is not set.
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int getOperandConstraint(unsigned OpNum,
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TOI::OperandConstraint Constraint) const {
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assert((OpNum < NumOperands || isVariadic()) &&
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"Invalid operand # of TargetInstrInfo");
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if (OpNum < NumOperands &&
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(OpInfo[OpNum].Constraints & (1 << Constraint))) {
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unsigned Pos = 16 + Constraint * 4;
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return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
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}
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return -1;
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}
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/// findTiedToSrcOperand - Returns the operand that is tied to the specified
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/// dest operand. Returns -1 if there isn't one.
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int findTiedToSrcOperand(unsigned OpNum) const;
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/// getOpcode - Return the opcode number for this descriptor.
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unsigned getOpcode() const {
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return Opcode;
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}
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/// getName - Return the name of the record in the .td file for this
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/// instruction, for example "ADD8ri".
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const char *getName() const {
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return Name;
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}
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/// getNumOperands - Return the number of declared MachineOperands for this
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/// MachineInstruction. Note that variadic (isVariadic() returns true)
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/// instructions may have additional operands at the end of the list, and note
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/// that the machine instruction may include implicit register def/uses as
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/// well.
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unsigned getNumOperands() const {
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return NumOperands;
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}
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/// getNumDefs - Return the number of MachineOperands that are register
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/// definitions. Register definitions always occur at the start of the
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/// machine operand list. This is the number of "outs" in the .td file.
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unsigned getNumDefs() const {
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return NumDefs;
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}
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/// isVariadic - Return true if this instruction can have a variable number of
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/// operands. In this case, the variable operands will be after the normal
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/// operands but before the implicit definitions and uses (if any are
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/// present).
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bool isVariadic() const {
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return Flags & (1 << TID::Variadic);
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}
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/// hasOptionalDef - Set if this instruction has an optional definition, e.g.
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/// ARM instructions which can set condition code if 's' bit is set.
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bool hasOptionalDef() const {
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return Flags & (1 << TID::HasOptionalDef);
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}
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/// getImplicitUses - Return a list of machine operands that are potentially
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/// read by any instance of this machine instruction. For example, on X86,
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/// the "adc" instruction adds two register operands and adds the carry bit in
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/// from the flags register. In this case, the instruction is marked as
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/// implicitly reading the flags. Likewise, the variable shift instruction on
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/// X86 is marked as implicitly reading the 'CL' register, which it always
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/// does.
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///
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/// This method returns null if the instruction has no implicit uses.
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const unsigned *getImplicitUses() const {
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return ImplicitUses;
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}
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/// getImplicitDefs - Return a list of machine operands that are potentially
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/// written by any instance of this machine instruction. For example, on X86,
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/// many instructions implicitly set the flags register. In this case, they
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/// are marked as setting the FLAGS. Likewise, many instructions always
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/// deposit their result in a physical register. For example, the X86 divide
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/// instruction always deposits the quotient and remainder in the EAX/EDX
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/// registers. For that instruction, this will return a list containing the
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/// EAX/EDX/EFLAGS registers.
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///
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/// This method returns null if the instruction has no implicit uses.
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const unsigned *getImplicitDefs() const {
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return ImplicitDefs;
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}
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/// getSchedClass - Return the scheduling class for this instruction. The
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/// scheduling class is an index into the InstrItineraryData table. This
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/// returns zero if there is no known scheduling information for the
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/// instruction.
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///
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unsigned getSchedClass() const {
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return SchedClass;
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}
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bool isReturn() const {
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return Flags & (1 << TID::Return);
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}
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bool isCall() const {
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return Flags & (1 << TID::Call);
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}
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/// isImplicitDef - Return true if this is an "IMPLICIT_DEF" instruction,
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/// which defines a register to an unspecified value. These basically
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/// correspond to x = undef.
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bool isImplicitDef() const {
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return Flags & (1 << TID::ImplicitDef);
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}
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/// isBarrier - Returns true if the specified instruction stops control flow
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/// from executing the instruction immediately following it. Examples include
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/// unconditional branches and return instructions.
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bool isBarrier() const {
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return Flags & (1 << TID::Barrier);
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}
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/// isTerminator - Returns true if this instruction part of the terminator for
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/// a basic block. Typically this is things like return and branch
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/// instructions.
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///
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/// Various passes use this to insert code into the bottom of a basic block,
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/// but before control flow occurs.
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bool isTerminator() const {
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return Flags & (1 << TID::Terminator);
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}
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/// isBranch - Returns true if this is a conditional, unconditional, or
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/// indirect branch. Predicates below can be used to discriminate between
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/// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
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/// get more information.
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bool isBranch() const {
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return Flags & (1 << TID::Branch);
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}
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/// isIndirectBranch - Return true if this is an indirect branch, such as a
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/// branch through a register.
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bool isIndirectBranch() const {
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return Flags & (1 << TID::IndirectBranch);
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}
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/// isConditionalBranch - Return true if this is a branch which may fall
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/// through to the next instruction or may transfer control flow to some other
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/// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
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/// information about this branch.
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bool isConditionalBranch() const {
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return isBranch() & !isBarrier() & !isIndirectBranch();
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}
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/// isUnconditionalBranch - Return true if this is a branch which always
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/// transfers control flow to some other block. The
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/// TargetInstrInfo::AnalyzeBranch method can be used to get more information
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/// about this branch.
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bool isUnconditionalBranch() const {
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return isBranch() & isBarrier() & !isIndirectBranch();
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}
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// isPredicable - Return true if this instruction has a predicate operand that
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// controls execution. It may be set to 'always', or may be set to other
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/// values. There are various methods in TargetInstrInfo that can be used to
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/// control and modify the predicate in this instruction.
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bool isPredicable() const {
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return Flags & (1 << TID::Predicable);
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}
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/// isNotDuplicable - Return true if this instruction cannot be safely
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/// duplicated. For example, if the instruction has a unique labels attached
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/// to it, duplicating it would cause multiple definition errors.
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bool isNotDuplicable() const {
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return Flags & (1 << TID::NotDuplicable);
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}
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/// hasDelaySlot - Returns true if the specified instruction has a delay slot
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/// which must be filled by the code generator.
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bool hasDelaySlot() const {
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return Flags & (1 << TID::DelaySlot);
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}
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/// isSimpleLoad - Return true for instructions that are simple loads from
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/// memory. This should only be set on instructions that load a value from
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/// memory and return it in their only virtual register definition.
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/// Instructions that return a value loaded from memory and then modified in
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/// some way should not return true for this.
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bool isSimpleLoad() const {
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return Flags & (1 << TID::SimpleLoad);
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}
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//===--------------------------------------------------------------------===//
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// Side Effect Analysis
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//===--------------------------------------------------------------------===//
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/// mayStore - Return true if this instruction could possibly modify memory.
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/// Instructions with this flag set are not necessarily simple store
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/// instructions, they may store a modified value based on their operands, or
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/// may not actually modify anything, for example.
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bool mayStore() const {
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return Flags & (1 << TID::MayStore);
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}
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// TODO: mayLoad.
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/// hasNoSideEffects - Return true if all instances of this instruction are
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/// guaranteed to have no side effects other than:
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/// 1. The register operands that are def/used by the MachineInstr.
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/// 2. Registers that are implicitly def/used by the MachineInstr.
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/// 3. Memory Accesses captured by mayLoad() or mayStore().
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///
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/// Examples of other side effects would be calling a function, modifying
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/// 'invisible' machine state like a control register, etc.
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///
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/// If some instances of this instruction are side-effect free but others are
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/// not, the hasConditionalSideEffects() property should return true, not this
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/// one.
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///
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/// Note that you should not call this method directly, instead, call the
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/// TargetInstrInfo::hasUnmodelledSideEffects method, which handles analysis
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/// of the machine instruction.
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bool hasNoSideEffects() const {
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return Flags & (1 << TID::NeverHasSideEffects);
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}
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/// hasConditionalSideEffects - Return true if some instances of this
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/// instruction are guaranteed to have no side effects other than those listed
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/// for hasNoSideEffects(). To determine whether a specific machineinstr has
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/// side effects, the TargetInstrInfo::isReallySideEffectFree virtual method
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/// is invoked to decide.
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///
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/// Note that you should not call this method directly, instead, call the
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/// TargetInstrInfo::hasUnmodelledSideEffects method, which handles analysis
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/// of the machine instruction.
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bool hasConditionalSideEffects() const {
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return Flags & (1 << TID::MayHaveSideEffects);
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}
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//===--------------------------------------------------------------------===//
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// Flags that indicate whether an instruction can be modified by a method.
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//===--------------------------------------------------------------------===//
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/// isCommutable - Return true if this may be a 2- or 3-address
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/// instruction (of the form "X = op Y, Z, ..."), which produces the same
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/// result if Y and Z are exchanged. If this flag is set, then the
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/// TargetInstrInfo::commuteInstruction method may be used to hack on the
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/// instruction.
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///
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/// Note that this flag may be set on instructions that are only commutable
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/// sometimes. In these cases, the call to commuteInstruction will fail.
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/// Also note that some instructions require non-trivial modification to
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/// commute them.
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bool isCommutable() const {
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return Flags & (1 << TID::Commutable);
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}
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/// isConvertibleTo3Addr - Return true if this is a 2-address instruction
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/// which can be changed into a 3-address instruction if needed. Doing this
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/// transformation can be profitable in the register allocator, because it
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/// means that the instruction can use a 2-address form if possible, but
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/// degrade into a less efficient form if the source and dest register cannot
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/// be assigned to the same register. For example, this allows the x86
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/// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
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/// is the same speed as the shift but has bigger code size.
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///
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/// If this returns true, then the target must implement the
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/// TargetInstrInfo::convertToThreeAddress method for this instruction, which
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/// is allowed to fail if the transformation isn't valid for this specific
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/// instruction (e.g. shl reg, 4 on x86).
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///
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bool isConvertibleTo3Addr() const {
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return Flags & (1 << TID::ConvertibleTo3Addr);
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}
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/// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
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/// custom insertion support when the DAG scheduler is inserting it into a
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/// machine basic block. If this is true for the instruction, it basically
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/// means that it is a pseudo instruction used at SelectionDAG time that is
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/// expanded out into magic code by the target when MachineInstrs are formed.
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///
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/// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
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/// is used to insert this into the MachineBasicBlock.
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bool usesCustomDAGSchedInsertionHook() const {
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return Flags & (1 << TID::UsesCustomDAGSchedInserter);
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}
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/// isRematerializable - Returns true if this instruction is a candidate for
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/// remat. This flag is deprecated, please don't use it anymore. If this
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/// flag is set, the isReallyTriviallyReMaterializable() method is called to
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/// verify the instruction is really rematable.
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bool isRematerializable() const {
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return Flags & (1 << TID::Rematerializable);
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}
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};
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//---------------------------------------------------------------------------
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///
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/// TargetInstrInfo - Interface to description of machine instructions
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///
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class TargetInstrInfo {
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const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
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unsigned NumOpcodes; // Number of entries in the desc array
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TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
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void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
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public:
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TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
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virtual ~TargetInstrInfo();
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// Invariant opcodes: All instruction sets have these as their low opcodes.
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enum {
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PHI = 0,
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INLINEASM = 1,
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LABEL = 2,
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EXTRACT_SUBREG = 3,
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INSERT_SUBREG = 4
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};
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unsigned getNumOpcodes() const { return NumOpcodes; }
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/// get - Return the machine instruction descriptor that corresponds to the
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/// specified instruction opcode.
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///
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const TargetInstrDesc &get(unsigned Opcode) const {
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assert(Opcode < NumOpcodes && "Invalid opcode!");
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return Descriptors[Opcode];
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}
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/// isTriviallyReMaterializable - Return true if the instruction is trivially
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/// rematerializable, meaning it has no side effects and requires no operands
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/// that aren't always available.
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bool isTriviallyReMaterializable(MachineInstr *MI) const {
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return MI->getDesc().isRematerializable() &&
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isReallyTriviallyReMaterializable(MI);
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}
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/// hasUnmodelledSideEffects - Returns true if the instruction has side
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/// effects that are not captured by any operands of the instruction or other
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/// flags.
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bool hasUnmodelledSideEffects(MachineInstr *MI) const {
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const TargetInstrDesc &TID = MI->getDesc();
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if (TID.hasNoSideEffects()) return false;
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if (!TID.hasConditionalSideEffects()) return true;
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return !isReallySideEffectFree(MI); // May have side effects
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}
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protected:
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/// isReallyTriviallyReMaterializable - For instructions with opcodes for
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/// which the M_REMATERIALIZABLE flag is set, this function tests whether the
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/// instruction itself is actually trivially rematerializable, considering
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/// its operands. This is used for targets that have instructions that are
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/// only trivially rematerializable for specific uses. This predicate must
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/// return false if the instruction has any side effects other than
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/// producing a value, or if it requres any address registers that are not
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/// always available.
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virtual bool isReallyTriviallyReMaterializable(MachineInstr *MI) const {
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return true;
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}
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/// isReallySideEffectFree - If the M_MAY_HAVE_SIDE_EFFECTS flag is set, this
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/// method is called to determine if the specific instance of this
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/// instruction has side effects. This is useful in cases of instructions,
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/// like loads, which generally always have side effects. A load from a
|
|
/// constant pool doesn't have side effects, though. So we need to
|
|
/// differentiate it from the general case.
|
|
virtual bool isReallySideEffectFree(MachineInstr *MI) const {
|
|
return false;
|
|
}
|
|
public:
|
|
/// Return true if the instruction is a register to register move
|
|
/// and leave the source and dest operands in the passed parameters.
|
|
virtual bool isMoveInstr(const MachineInstr& MI,
|
|
unsigned& sourceReg,
|
|
unsigned& destReg) const {
|
|
return false;
|
|
}
|
|
|
|
/// isLoadFromStackSlot - If the specified machine instruction is a direct
|
|
/// load from a stack slot, return the virtual or physical register number of
|
|
/// the destination along with the FrameIndex of the loaded stack slot. If
|
|
/// not, return 0. This predicate must return 0 if the instruction has
|
|
/// any side effects other than loading from the stack slot.
|
|
virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
|
|
return 0;
|
|
}
|
|
|
|
/// isStoreToStackSlot - If the specified machine instruction is a direct
|
|
/// store to a stack slot, return the virtual or physical register number of
|
|
/// the source reg along with the FrameIndex of the loaded stack slot. If
|
|
/// not, return 0. This predicate must return 0 if the instruction has
|
|
/// any side effects other than storing to the stack slot.
|
|
virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
|
|
return 0;
|
|
}
|
|
|
|
/// convertToThreeAddress - This method must be implemented by targets that
|
|
/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
|
|
/// may be able to convert a two-address instruction into one or more true
|
|
/// three-address instructions on demand. This allows the X86 target (for
|
|
/// example) to convert ADD and SHL instructions into LEA instructions if they
|
|
/// would require register copies due to two-addressness.
|
|
///
|
|
/// This method returns a null pointer if the transformation cannot be
|
|
/// performed, otherwise it returns the last new instruction.
|
|
///
|
|
virtual MachineInstr *
|
|
convertToThreeAddress(MachineFunction::iterator &MFI,
|
|
MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const {
|
|
return 0;
|
|
}
|
|
|
|
/// commuteInstruction - If a target has any instructions that are commutable,
|
|
/// but require converting to a different instruction or making non-trivial
|
|
/// changes to commute them, this method can overloaded to do this. The
|
|
/// default implementation of this method simply swaps the first two operands
|
|
/// of MI and returns it.
|
|
///
|
|
/// If a target wants to make more aggressive changes, they can construct and
|
|
/// return a new machine instruction. If an instruction cannot commute, it
|
|
/// can also return null.
|
|
///
|
|
virtual MachineInstr *commuteInstruction(MachineInstr *MI) const = 0;
|
|
|
|
/// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
|
|
/// true if it cannot be understood (e.g. it's a switch dispatch or isn't
|
|
/// implemented for a target). Upon success, this returns false and returns
|
|
/// with the following information in various cases:
|
|
///
|
|
/// 1. If this block ends with no branches (it just falls through to its succ)
|
|
/// just return false, leaving TBB/FBB null.
|
|
/// 2. If this block ends with only an unconditional branch, it sets TBB to be
|
|
/// the destination block.
|
|
/// 3. If this block ends with an conditional branch and it falls through to
|
|
/// an successor block, it sets TBB to be the branch destination block and a
|
|
/// list of operands that evaluate the condition. These
|
|
/// operands can be passed to other TargetInstrInfo methods to create new
|
|
/// branches.
|
|
/// 4. If this block ends with an conditional branch and an unconditional
|
|
/// block, it returns the 'true' destination in TBB, the 'false' destination
|
|
/// in FBB, and a list of operands that evaluate the condition. These
|
|
/// operands can be passed to other TargetInstrInfo methods to create new
|
|
/// branches.
|
|
///
|
|
/// Note that RemoveBranch and InsertBranch must be implemented to support
|
|
/// cases where this method returns success.
|
|
///
|
|
virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
|
|
MachineBasicBlock *&FBB,
|
|
std::vector<MachineOperand> &Cond) const {
|
|
return true;
|
|
}
|
|
|
|
/// RemoveBranch - Remove the branching code at the end of the specific MBB.
|
|
/// this is only invoked in cases where AnalyzeBranch returns success. It
|
|
/// returns the number of instructions that were removed.
|
|
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
|
|
assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
|
|
return 0;
|
|
}
|
|
|
|
/// InsertBranch - Insert a branch into the end of the specified
|
|
/// MachineBasicBlock. This operands to this method are the same as those
|
|
/// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
|
|
/// returns success and when an unconditional branch (TBB is non-null, FBB is
|
|
/// null, Cond is empty) needs to be inserted. It returns the number of
|
|
/// instructions inserted.
|
|
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
|
MachineBasicBlock *FBB,
|
|
const std::vector<MachineOperand> &Cond) const {
|
|
assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
|
|
return 0;
|
|
}
|
|
|
|
/// copyRegToReg - Add a copy between a pair of registers
|
|
virtual void copyRegToReg(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
unsigned DestReg, unsigned SrcReg,
|
|
const TargetRegisterClass *DestRC,
|
|
const TargetRegisterClass *SrcRC) const {
|
|
assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
|
|
}
|
|
|
|
virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
unsigned SrcReg, bool isKill, int FrameIndex,
|
|
const TargetRegisterClass *RC) const {
|
|
assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
|
|
}
|
|
|
|
virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
|
|
SmallVectorImpl<MachineOperand> &Addr,
|
|
const TargetRegisterClass *RC,
|
|
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
|
assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!");
|
|
}
|
|
|
|
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
unsigned DestReg, int FrameIndex,
|
|
const TargetRegisterClass *RC) const {
|
|
assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
|
|
}
|
|
|
|
virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
|
SmallVectorImpl<MachineOperand> &Addr,
|
|
const TargetRegisterClass *RC,
|
|
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
|
assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!");
|
|
}
|
|
|
|
/// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
|
|
/// saved registers and returns true if it isn't possible / profitable to do
|
|
/// so by issuing a series of store instructions via
|
|
/// storeRegToStackSlot(). Returns false otherwise.
|
|
virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
const std::vector<CalleeSavedInfo> &CSI) const {
|
|
return false;
|
|
}
|
|
|
|
/// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
|
|
/// saved registers and returns true if it isn't possible / profitable to do
|
|
/// so by issuing a series of load instructions via loadRegToStackSlot().
|
|
/// Returns false otherwise.
|
|
virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
const std::vector<CalleeSavedInfo> &CSI) const {
|
|
return false;
|
|
}
|
|
|
|
/// foldMemoryOperand - Attempt to fold a load or store of the specified stack
|
|
/// slot into the specified machine instruction for the specified operand(s).
|
|
/// If this is possible, a new instruction is returned with the specified
|
|
/// operand folded, otherwise NULL is returned. The client is responsible for
|
|
/// removing the old instruction and adding the new one in the instruction
|
|
/// stream.
|
|
virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
|
|
SmallVectorImpl<unsigned> &Ops,
|
|
int FrameIndex) const {
|
|
return 0;
|
|
}
|
|
|
|
/// foldMemoryOperand - Same as the previous version except it allows folding
|
|
/// of any load and store from / to any address, not just from a specific
|
|
/// stack slot.
|
|
virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
|
|
SmallVectorImpl<unsigned> &Ops,
|
|
MachineInstr* LoadMI) const {
|
|
return 0;
|
|
}
|
|
|
|
/// canFoldMemoryOperand - Returns true if the specified load / store is
|
|
/// folding is possible.
|
|
virtual
|
|
bool canFoldMemoryOperand(MachineInstr *MI,
|
|
SmallVectorImpl<unsigned> &Ops) const{
|
|
return false;
|
|
}
|
|
|
|
/// unfoldMemoryOperand - Separate a single instruction which folded a load or
|
|
/// a store or a load and a store into two or more instruction. If this is
|
|
/// possible, returns true as well as the new instructions by reference.
|
|
virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
|
|
unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
|
|
SmallVectorImpl<MachineInstr*> &NewMIs) const{
|
|
return false;
|
|
}
|
|
|
|
virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
|
|
SmallVectorImpl<SDNode*> &NewNodes) const {
|
|
return false;
|
|
}
|
|
|
|
/// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
|
|
/// instruction after load / store are unfolded from an instruction of the
|
|
/// specified opcode. It returns zero if the specified unfolding is not
|
|
/// possible.
|
|
virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
|
|
bool UnfoldLoad, bool UnfoldStore) const {
|
|
return 0;
|
|
}
|
|
|
|
/// BlockHasNoFallThrough - Return true if the specified block does not
|
|
/// fall-through into its successor block. This is primarily used when a
|
|
/// branch is unanalyzable. It is useful for things like unconditional
|
|
/// indirect branches (jump tables).
|
|
virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
|
|
return false;
|
|
}
|
|
|
|
/// ReverseBranchCondition - Reverses the branch condition of the specified
|
|
/// condition list, returning false on success and true if it cannot be
|
|
/// reversed.
|
|
virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
|
|
return true;
|
|
}
|
|
|
|
/// insertNoop - Insert a noop into the instruction stream at the specified
|
|
/// point.
|
|
virtual void insertNoop(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI) const {
|
|
assert(0 && "Target didn't implement insertNoop!");
|
|
abort();
|
|
}
|
|
|
|
/// isPredicated - Returns true if the instruction is already predicated.
|
|
///
|
|
virtual bool isPredicated(const MachineInstr *MI) const {
|
|
return false;
|
|
}
|
|
|
|
/// isUnpredicatedTerminator - Returns true if the instruction is a
|
|
/// terminator instruction that has not been predicated.
|
|
virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
|
|
|
|
/// PredicateInstruction - Convert the instruction into a predicated
|
|
/// instruction. It returns true if the operation was successful.
|
|
virtual
|
|
bool PredicateInstruction(MachineInstr *MI,
|
|
const std::vector<MachineOperand> &Pred) const = 0;
|
|
|
|
/// SubsumesPredicate - Returns true if the first specified predicate
|
|
/// subsumes the second, e.g. GE subsumes GT.
|
|
virtual
|
|
bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
|
|
const std::vector<MachineOperand> &Pred2) const {
|
|
return false;
|
|
}
|
|
|
|
/// DefinesPredicate - If the specified instruction defines any predicate
|
|
/// or condition code register(s) used for predication, returns true as well
|
|
/// as the definition predicate(s) by reference.
|
|
virtual bool DefinesPredicate(MachineInstr *MI,
|
|
std::vector<MachineOperand> &Pred) const {
|
|
return false;
|
|
}
|
|
|
|
/// getPointerRegClass - Returns a TargetRegisterClass used for pointer
|
|
/// values.
|
|
virtual const TargetRegisterClass *getPointerRegClass() const {
|
|
assert(0 && "Target didn't implement getPointerRegClass!");
|
|
abort();
|
|
return 0; // Must return a value in order to compile with VS 2005
|
|
}
|
|
};
|
|
|
|
/// TargetInstrInfoImpl - This is the default implementation of
|
|
/// TargetInstrInfo, which just provides a couple of default implementations
|
|
/// for various methods. This separated out because it is implemented in
|
|
/// libcodegen, not in libtarget.
|
|
class TargetInstrInfoImpl : public TargetInstrInfo {
|
|
protected:
|
|
TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
|
|
: TargetInstrInfo(desc, NumOpcodes) {}
|
|
public:
|
|
virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
|
|
virtual bool PredicateInstruction(MachineInstr *MI,
|
|
const std::vector<MachineOperand> &Pred) const;
|
|
|
|
};
|
|
|
|
} // End llvm namespace
|
|
|
|
#endif
|