mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-03-22 10:36:10 +00:00
rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
682b8aed07
commit
749c6f6b5e
@ -20,7 +20,7 @@
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namespace llvm {
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class TargetInstrDescriptor;
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class TargetInstrDesc;
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template <typename T> struct ilist_traits;
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template <typename T> struct ilist;
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@ -29,7 +29,7 @@ template <typename T> struct ilist;
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/// MachineInstr - Representation of each machine instruction.
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///
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class MachineInstr {
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const TargetInstrDescriptor *TID; // Instruction descriptor.
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const TargetInstrDesc *TID; // Instruction descriptor.
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unsigned short NumImplicitOps; // Number of implicit operands (which
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// are determined at construction time).
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@ -54,14 +54,14 @@ public:
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/// MachineInstr ctor - This constructor create a MachineInstr and add the
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/// implicit operands. It reserves space for number of operands specified by
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/// TargetInstrDescriptor.
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explicit MachineInstr(const TargetInstrDescriptor &TID, bool NoImp = false);
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/// TargetInstrDesc.
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explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false);
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/// MachineInstr ctor - Work exactly the same as the ctor above, except that
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/// the MachineInstr is created and added to the end of the specified basic
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/// block.
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///
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MachineInstr(MachineBasicBlock *MBB, const TargetInstrDescriptor &TID);
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MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID);
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~MachineInstr();
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@ -70,7 +70,7 @@ public:
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/// getDesc - Returns the target instruction descriptor of this
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/// MachineInstr.
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const TargetInstrDescriptor *getDesc() const { return TID; }
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const TargetInstrDesc &getDesc() const { return *TID; }
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/// getOpcode - Returns the opcode of this MachineInstr.
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///
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@ -166,7 +166,7 @@ public:
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/// setInstrDescriptor - Replace the instruction descriptor (thus opcode) of
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/// the current instruction with a new one.
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///
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void setInstrDescriptor(const TargetInstrDescriptor &tid) { TID = &tid; }
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void setInstrDescriptor(const TargetInstrDesc &tid) { TID = &tid; }
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/// RemoveOperand - Erase an operand from an instruction, leaving it with one
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/// fewer operand than it started with.
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@ -22,7 +22,7 @@
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namespace llvm {
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class TargetInstrDescriptor;
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class TargetInstrDesc;
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class MachineInstrBuilder {
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MachineInstr *MI;
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@ -88,14 +88,14 @@ public:
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/// BuildMI - Builder interface. Specify how to create the initial instruction
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/// itself.
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///
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inline MachineInstrBuilder BuildMI(const TargetInstrDescriptor &TID) {
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inline MachineInstrBuilder BuildMI(const TargetInstrDesc &TID) {
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return MachineInstrBuilder(new MachineInstr(TID));
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}
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/// BuildMI - This version of the builder sets up the first operand as a
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/// destination virtual register.
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///
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inline MachineInstrBuilder BuildMI(const TargetInstrDescriptor &TID,
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inline MachineInstrBuilder BuildMI(const TargetInstrDesc &TID,
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unsigned DestReg) {
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return MachineInstrBuilder(new MachineInstr(TID)).addReg(DestReg, true);
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}
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@ -106,7 +106,7 @@ inline MachineInstrBuilder BuildMI(const TargetInstrDescriptor &TID,
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///
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inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
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MachineBasicBlock::iterator I,
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const TargetInstrDescriptor &TID,
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const TargetInstrDesc &TID,
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unsigned DestReg) {
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MachineInstr *MI = new MachineInstr(TID);
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BB.insert(I, MI);
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@ -119,7 +119,7 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
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///
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inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
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MachineBasicBlock::iterator I,
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const TargetInstrDescriptor &TID) {
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const TargetInstrDesc &TID) {
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MachineInstr *MI = new MachineInstr(TID);
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BB.insert(I, MI);
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return MachineInstrBuilder(MI);
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@ -130,7 +130,7 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
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/// destination register.
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///
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inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
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const TargetInstrDescriptor &TID) {
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const TargetInstrDesc &TID) {
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return BuildMI(*BB, BB->end(), TID);
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}
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@ -139,7 +139,7 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
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/// operand as a destination virtual register.
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///
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inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
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const TargetInstrDescriptor &TID,
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const TargetInstrDesc &TID,
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unsigned DestReg) {
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return BuildMI(*BB, BB->end(), TID, DestReg);
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}
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@ -31,7 +31,7 @@ namespace llvm {
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class SelectionDAG;
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class SelectionDAGISel;
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class TargetInstrInfo;
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class TargetInstrDescriptor;
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class TargetInstrDesc;
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class TargetMachine;
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class TargetRegisterClass;
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@ -335,7 +335,7 @@ namespace llvm {
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DenseMap<SDOperand, unsigned> &VRBaseMap);
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void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
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const TargetInstrDescriptor &II,
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const TargetInstrDesc &II,
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DenseMap<SDOperand, unsigned> &VRBaseMap);
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void EmitSchedule();
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@ -353,7 +353,7 @@ namespace llvm {
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DenseMap<SDOperand, unsigned> &VRBaseMap);
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void AddOperand(MachineInstr *MI, SDOperand Op, unsigned IIOpNum,
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const TargetInstrDescriptor *II,
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const TargetInstrDesc *II,
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DenseMap<SDOperand, unsigned> &VRBaseMap);
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};
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@ -82,10 +82,10 @@ public:
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// Machine Instruction Flags and Description
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//===----------------------------------------------------------------------===//
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/// TargetInstrDescriptor flags - These should be considered private to the
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/// implementation of the TargetInstrDescriptor class. Clients should use the
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/// predicate methods on TargetInstrDescriptor, not use these directly. These
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/// all correspond to bitfields in the TargetInstrDescriptor::Flags field.
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/// TargetInstrDesc flags - These should be considered private to the
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/// implementation of the TargetInstrDesc class. Clients should use the
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/// predicate methods on TargetInstrDesc, not use these directly. These
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/// all correspond to bitfields in the TargetInstrDesc::Flags field.
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namespace TID {
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enum {
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Variadic = 0,
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@ -111,12 +111,12 @@ namespace TID {
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};
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}
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/// TargetInstrDescriptor - Describe properties that are true of each
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/// TargetInstrDesc - Describe properties that are true of each
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/// instruction in the target description file. This captures information about
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/// side effects, register use and many other things. There is one instance of
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/// this struct for each target instruction class, and the MachineInstr class
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/// points to this struct directly to describe itself.
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class TargetInstrDescriptor {
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class TargetInstrDesc {
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public:
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unsigned short Opcode; // The opcode number.
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unsigned short NumOperands; // Num of args (may be more if variable_ops)
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@ -147,6 +147,11 @@ public:
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/// dest operand. Returns -1 if there isn't one.
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int findTiedToSrcOperand(unsigned OpNum) const;
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/// getOpcode - Return the opcode number for this descriptor.
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unsigned getOpcode() const {
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return Opcode;
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}
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/// getName - Return the name of the record in the .td file for this
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/// instruction, for example "ADD8ri".
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const char *getName() const {
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@ -421,14 +426,13 @@ public:
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/// TargetInstrInfo - Interface to description of machine instructions
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///
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class TargetInstrInfo {
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const TargetInstrDescriptor* desc; // raw array to allow static init'n
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unsigned NumOpcodes; // number of entries in the desc array
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unsigned numRealOpCodes; // number of non-dummy op codes
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const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
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unsigned NumOpcodes; // Number of entries in the desc array
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TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
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void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
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public:
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TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
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TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
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virtual ~TargetInstrInfo();
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// Invariant opcodes: All instruction sets have these as their low opcodes.
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@ -445,16 +449,16 @@ public:
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/// get - Return the machine instruction descriptor that corresponds to the
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/// specified instruction opcode.
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///
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const TargetInstrDescriptor& get(unsigned Opcode) const {
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assert(Opcode < NumOpcodes);
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return desc[Opcode];
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const TargetInstrDesc &get(unsigned Opcode) const {
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assert(Opcode < NumOpcodes && "Invalid opcode!");
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return Descriptors[Opcode];
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}
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/// isTriviallyReMaterializable - Return true if the instruction is trivially
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/// rematerializable, meaning it has no side effects and requires no operands
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/// that aren't always available.
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bool isTriviallyReMaterializable(MachineInstr *MI) const {
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return MI->getDesc()->isRematerializable() &&
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return MI->getDesc().isRematerializable() &&
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isReallyTriviallyReMaterializable(MI);
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}
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@ -462,9 +466,9 @@ public:
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/// effects that are not captured by any operands of the instruction or other
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/// flags.
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bool hasUnmodelledSideEffects(MachineInstr *MI) const {
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const TargetInstrDescriptor *TID = MI->getDesc();
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if (TID->hasNoSideEffects()) return false;
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if (!TID->hasConditionalSideEffects()) return true;
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const TargetInstrDesc &TID = MI->getDesc();
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if (TID.hasNoSideEffects()) return false;
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if (!TID.hasConditionalSideEffects()) return true;
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return !isReallySideEffectFree(MI); // May have side effects
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}
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protected:
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@ -773,7 +777,7 @@ public:
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/// libcodegen, not in libtarget.
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class TargetInstrInfoImpl : public TargetInstrInfo {
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protected:
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TargetInstrInfoImpl(const TargetInstrDescriptor *desc, unsigned NumOpcodes)
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TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
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: TargetInstrInfo(desc, NumOpcodes) {}
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public:
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virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
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@ -24,7 +24,6 @@ class TargetAsmInfo;
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class TargetData;
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class TargetSubtarget;
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class TargetInstrInfo;
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class TargetInstrDescriptor;
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class TargetJITInfo;
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class TargetLowering;
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class TargetFrameInfo;
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@ -349,10 +349,10 @@ static unsigned EstimateRuntime(MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator E) {
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unsigned Time = 0;
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for (; I != E; ++I) {
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const TargetInstrDescriptor *TID = I->getDesc();
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if (TID->isCall())
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const TargetInstrDesc &TID = I->getDesc();
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if (TID.isCall())
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Time += 10;
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else if (TID->isSimpleLoad() || TID->mayStore())
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else if (TID.isSimpleLoad() || TID.mayStore())
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Time += 2;
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else
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++Time;
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@ -778,7 +778,7 @@ static bool IsBetterFallthrough(MachineBasicBlock *MBB1,
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MachineInstr *MBB1I = --MBB1->end();
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MachineInstr *MBB2I = --MBB2->end();
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return MBB2I->getDesc()->isCall() && !MBB1I->getDesc()->isCall();
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return MBB2I->getDesc().isCall() && !MBB1I->getDesc().isCall();
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}
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/// OptimizeBlock - Analyze and optimize control flow related to the specified
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@ -958,7 +958,7 @@ void BranchFolder::OptimizeBlock(MachineBasicBlock *MBB) {
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// If this branch is the only thing in its block, see if we can forward
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// other blocks across it.
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if (CurTBB && CurCond.empty() && CurFBB == 0 &&
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MBB->begin()->getDesc()->isBranch() && CurTBB != MBB) {
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MBB->begin()->getDesc().isBranch() && CurTBB != MBB) {
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// This block may contain just an unconditional branch. Because there can
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// be 'non-branch terminators' in the block, try removing the branch and
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// then seeing if the block is empty.
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@ -359,7 +359,7 @@ void MachineCodeAnalysis::FindSafePoints(MachineFunction &MF) {
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BBE = MF.end(); BBI != BBE; ++BBI)
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for (MachineBasicBlock::iterator MI = BBI->begin(),
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ME = BBI->end(); MI != ME; ++MI)
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if (MI->getDesc()->isCall())
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if (MI->getDesc().isCall())
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VisitCallPoint(*MI);
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}
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@ -3153,7 +3153,7 @@ private:
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for (MachineBasicBlock::const_iterator MI = I->begin(), E = I->end();
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MI != E; ++MI) {
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if (MI->getOpcode() != TargetInstrInfo::LABEL) {
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SawPotentiallyThrowing |= MI->getDesc()->isCall();
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SawPotentiallyThrowing |= MI->getDesc().isCall();
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continue;
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}
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@ -460,7 +460,7 @@ MachineBasicBlock::iterator firstNonBranchInst(MachineBasicBlock *BB,
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MachineBasicBlock::iterator I = BB->end();
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while (I != BB->begin()) {
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--I;
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if (!I->getDesc()->isBranch())
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if (!I->getDesc().isBranch())
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break;
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}
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return I;
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@ -548,12 +548,12 @@ void IfConverter::ScanInstructions(BBInfo &BBI) {
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bool SeenCondBr = false;
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for (MachineBasicBlock::iterator I = BBI.BB->begin(), E = BBI.BB->end();
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I != E; ++I) {
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const TargetInstrDescriptor *TID = I->getDesc();
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if (TID->isNotDuplicable())
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const TargetInstrDesc &TID = I->getDesc();
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if (TID.isNotDuplicable())
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BBI.CannotBeCopied = true;
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bool isPredicated = TII->isPredicated(I);
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bool isCondBr = BBI.IsBrAnalyzable && TID->isConditionalBranch();
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bool isCondBr = BBI.IsBrAnalyzable && TID.isConditionalBranch();
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if (!isCondBr) {
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if (!isPredicated)
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@ -590,7 +590,7 @@ void IfConverter::ScanInstructions(BBInfo &BBI) {
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if (TII->DefinesPredicate(I, PredDefs))
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BBI.ClobbersPred = true;
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if (!TID->isPredicable()) {
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if (!TID.isPredicable()) {
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BBI.IsUnpredicable = true;
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return;
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}
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@ -1132,10 +1132,10 @@ void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
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bool IgnoreBr) {
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for (MachineBasicBlock::iterator I = FromBBI.BB->begin(),
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E = FromBBI.BB->end(); I != E; ++I) {
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const TargetInstrDescriptor *TID = I->getDesc();
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const TargetInstrDesc &TID = I->getDesc();
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bool isPredicated = TII->isPredicated(I);
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// Do not copy the end of the block branches.
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if (IgnoreBr && !isPredicated && TID->isBranch())
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if (IgnoreBr && !isPredicated && TID.isBranch())
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break;
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MachineInstr *MI = I->clone();
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@ -615,9 +615,9 @@ bool LiveIntervals::isReMaterializable(const LiveInterval &li,
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return false;
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isLoad = false;
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const TargetInstrDescriptor *TID = MI->getDesc();
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if (TID->isImplicitDef() || tii_->isTriviallyReMaterializable(MI)) {
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isLoad = TID->isSimpleLoad();
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const TargetInstrDesc &TID = MI->getDesc();
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if (TID.isImplicitDef() || tii_->isTriviallyReMaterializable(MI)) {
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isLoad = TID.isSimpleLoad();
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return true;
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}
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@ -679,9 +679,9 @@ bool LiveIntervals::tryFoldMemoryOperand(MachineInstr* &MI,
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SmallVector<unsigned, 2> &Ops,
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bool isSS, int Slot, unsigned Reg) {
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unsigned MRInfo = 0;
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const TargetInstrDescriptor *TID = MI->getDesc();
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const TargetInstrDesc &TID = MI->getDesc();
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// If it is an implicit def instruction, just delete it.
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if (TID->isImplicitDef()) {
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if (TID.isImplicitDef()) {
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RemoveMachineInstrFromMaps(MI);
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vrm.RemoveMachineInstrFromMaps(MI);
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MI->eraseFromParent();
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@ -699,7 +699,7 @@ bool LiveIntervals::tryFoldMemoryOperand(MachineInstr* &MI,
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MRInfo |= (unsigned)VirtRegMap::isMod;
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else {
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// Filter out two-address use operand(s).
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if (TID->getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
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if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
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MRInfo = VirtRegMap::isModRef;
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continue;
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}
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@ -1225,7 +1225,7 @@ addIntervalsForSpills(const LiveInterval &li,
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int LdSlot = 0;
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bool isLoadSS = DefIsReMat && tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
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bool isLoad = isLoadSS ||
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(DefIsReMat && (ReMatDefMI->getDesc()->isSimpleLoad()));
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(DefIsReMat && (ReMatDefMI->getDesc().isSimpleLoad()));
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bool IsFirstRange = true;
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for (LiveInterval::Ranges::const_iterator
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I = li.ranges.begin(), E = li.ranges.end(); I != E; ++I) {
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@ -1307,7 +1307,7 @@ addIntervalsForSpills(const LiveInterval &li,
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int LdSlot = 0;
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bool isLoadSS = DefIsReMat && tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
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bool isLoad = isLoadSS ||
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(DefIsReMat && ReMatDefMI->getDesc()->isSimpleLoad());
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(DefIsReMat && ReMatDefMI->getDesc().isSimpleLoad());
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rewriteInstructionsForSpills(li, TrySplit, I, ReMatOrigDefMI, ReMatDefMI,
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Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
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CanDelete, vrm, RegInfo, rc, ReMatIds, loopInfo,
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@ -1422,7 +1422,7 @@ addIntervalsForSpills(const LiveInterval &li,
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int LdSlot = 0;
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bool isLoadSS = tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
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// If the rematerializable def is a load, also try to fold it.
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if (isLoadSS || ReMatDefMI->getDesc()->isSimpleLoad())
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if (isLoadSS || ReMatDefMI->getDesc().isSimpleLoad())
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Folded = tryFoldMemoryOperand(MI, vrm, ReMatDefMI, index,
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Ops, isLoadSS, LdSlot, VReg);
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}
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@ -1450,7 +1450,7 @@ addIntervalsForSpills(const LiveInterval &li,
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MachineInstr *LastUse = getInstructionFromIndex(LastUseIdx);
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int UseIdx = LastUse->findRegisterUseOperandIdx(LI->reg);
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assert(UseIdx != -1);
|
||||
if (LastUse->getDesc()->getOperandConstraint(UseIdx, TOI::TIED_TO) ==
|
||||
if (LastUse->getDesc().getOperandConstraint(UseIdx, TOI::TIED_TO) ==
|
||||
-1) {
|
||||
LastUse->getOperand(UseIdx).setIsKill();
|
||||
vrm.addKillPoint(LI->reg, LastUseIdx);
|
||||
|
@ -535,7 +535,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
|
||||
|
||||
// Finally, if the last instruction in the block is a return, make sure to mark
|
||||
// it as using all of the live-out values in the function.
|
||||
if (!MBB->empty() && MBB->back().getDesc()->isReturn()) {
|
||||
if (!MBB->empty() && MBB->back().getDesc().isReturn()) {
|
||||
MachineInstr *Ret = &MBB->back();
|
||||
for (MachineRegisterInfo::liveout_iterator
|
||||
I = MF->getRegInfo().liveout_begin(),
|
||||
|
@ -132,9 +132,9 @@ void ilist_traits<MachineInstr>::transferNodesFromList(
|
||||
|
||||
MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() {
|
||||
iterator I = end();
|
||||
while (I != begin() && (--I)->getDesc()->isTerminator())
|
||||
while (I != begin() && (--I)->getDesc().isTerminator())
|
||||
; /*noop */
|
||||
if (I != end() && !I->getDesc()->isTerminator()) ++I;
|
||||
if (I != end() && !I->getDesc().isTerminator()) ++I;
|
||||
return I;
|
||||
}
|
||||
|
||||
@ -261,7 +261,7 @@ void MachineBasicBlock::ReplaceUsesOfBlockWith(MachineBasicBlock *Old,
|
||||
MachineBasicBlock::iterator I = end();
|
||||
while (I != begin()) {
|
||||
--I;
|
||||
if (!I->getDesc()->isTerminator()) break;
|
||||
if (!I->getDesc().isTerminator()) break;
|
||||
|
||||
// Scan the operands of this machine instruction, replacing any uses of Old
|
||||
// with New.
|
||||
|
@ -248,9 +248,9 @@ void MachineInstr::addImplicitDefUseOperands() {
|
||||
|
||||
/// MachineInstr ctor - This constructor create a MachineInstr and add the
|
||||
/// implicit operands. It reserves space for number of operands specified by
|
||||
/// TargetInstrDescriptor or the numOperands if it is not zero. (for
|
||||
/// TargetInstrDesc or the numOperands if it is not zero. (for
|
||||
/// instructions with variable number of operands).
|
||||
MachineInstr::MachineInstr(const TargetInstrDescriptor &tid, bool NoImp)
|
||||
MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
|
||||
: TID(&tid), NumImplicitOps(0), Parent(0) {
|
||||
if (!NoImp && TID->getImplicitDefs())
|
||||
for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
|
||||
@ -269,7 +269,7 @@ MachineInstr::MachineInstr(const TargetInstrDescriptor &tid, bool NoImp)
|
||||
/// MachineInstr is created and added to the end of the specified basic block.
|
||||
///
|
||||
MachineInstr::MachineInstr(MachineBasicBlock *MBB,
|
||||
const TargetInstrDescriptor &tid)
|
||||
const TargetInstrDesc &tid)
|
||||
: TID(&tid), NumImplicitOps(0), Parent(0) {
|
||||
assert(MBB && "Cannot use inserting ctor with null basic block!");
|
||||
if (TID->ImplicitDefs)
|
||||
@ -288,7 +288,7 @@ MachineInstr::MachineInstr(MachineBasicBlock *MBB,
|
||||
/// MachineInstr ctor - Copies MachineInstr arg exactly
|
||||
///
|
||||
MachineInstr::MachineInstr(const MachineInstr &MI) {
|
||||
TID = MI.getDesc();
|
||||
TID = &MI.getDesc();
|
||||
NumImplicitOps = MI.NumImplicitOps;
|
||||
Operands.reserve(MI.getNumOperands());
|
||||
|
||||
@ -537,10 +537,10 @@ MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
|
||||
/// operand list that is used to represent the predicate. It returns -1 if
|
||||
/// none is found.
|
||||
int MachineInstr::findFirstPredOperandIdx() const {
|
||||
const TargetInstrDescriptor *TID = getDesc();
|
||||
if (TID->isPredicable()) {
|
||||
const TargetInstrDesc &TID = getDesc();
|
||||
if (TID.isPredicable()) {
|
||||
for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
|
||||
if (TID->OpInfo[i].isPredicate())
|
||||
if (TID.OpInfo[i].isPredicate())
|
||||
return i;
|
||||
}
|
||||
|
||||
@ -550,14 +550,14 @@ int MachineInstr::findFirstPredOperandIdx() const {
|
||||
/// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
|
||||
/// to two addr elimination.
|
||||
bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const {
|
||||
const TargetInstrDescriptor *TID = getDesc();
|
||||
const TargetInstrDesc &TID = getDesc();
|
||||
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
|
||||
const MachineOperand &MO1 = getOperand(i);
|
||||
if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
|
||||
for (unsigned j = i+1; j < e; ++j) {
|
||||
const MachineOperand &MO2 = getOperand(j);
|
||||
if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
|
||||
TID->getOperandConstraint(j, TOI::TIED_TO) == (int)i)
|
||||
TID.getOperandConstraint(j, TOI::TIED_TO) == (int)i)
|
||||
return true;
|
||||
}
|
||||
}
|
||||
@ -587,10 +587,10 @@ void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
|
||||
|
||||
/// copyPredicates - Copies predicate operand(s) from MI.
|
||||
void MachineInstr::copyPredicates(const MachineInstr *MI) {
|
||||
const TargetInstrDescriptor *TID = MI->getDesc();
|
||||
if (TID->isPredicable()) {
|
||||
const TargetInstrDesc &TID = MI->getDesc();
|
||||
if (TID.isPredicable()) {
|
||||
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
||||
if (TID->OpInfo[i].isPredicate()) {
|
||||
if (TID.OpInfo[i].isPredicate()) {
|
||||
// Predicated operands must be last operands.
|
||||
addOperand(MI->getOperand(i));
|
||||
}
|
||||
@ -611,7 +611,7 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
|
||||
++StartOp; // Don't print this operand again!
|
||||
}
|
||||
|
||||
OS << getDesc()->Name;
|
||||
OS << getDesc().getName();
|
||||
|
||||
for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
|
||||
if (i != StartOp)
|
||||
|
@ -225,20 +225,20 @@ void MachineLICM::HoistRegion(MachineDomTreeNode *N) {
|
||||
bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
|
||||
DEBUG({
|
||||
DOUT << "--- Checking if we can hoist " << I;
|
||||
if (I.getDesc()->ImplicitUses) {
|
||||
if (I.getDesc().getImplicitUses()) {
|
||||
DOUT << " * Instruction has implicit uses:\n";
|
||||
|
||||
const MRegisterInfo *MRI = TM->getRegisterInfo();
|
||||
for (const unsigned *ImpUses = I.getDesc()->ImplicitUses;
|
||||
for (const unsigned *ImpUses = I.getDesc().getImplicitUses();
|
||||
*ImpUses; ++ImpUses)
|
||||
DOUT << " -> " << MRI->getName(*ImpUses) << "\n";
|
||||
}
|
||||
|
||||
if (I.getDesc()->ImplicitDefs) {
|
||||
if (I.getDesc().getImplicitDefs()) {
|
||||
DOUT << " * Instruction has implicit defines:\n";
|
||||
|
||||
const MRegisterInfo *MRI = TM->getRegisterInfo();
|
||||
for (const unsigned *ImpDefs = I.getDesc()->ImplicitDefs;
|
||||
for (const unsigned *ImpDefs = I.getDesc().getImplicitDefs();
|
||||
*ImpDefs; ++ImpDefs)
|
||||
DOUT << " -> " << MRI->getName(*ImpDefs) << "\n";
|
||||
}
|
||||
|
@ -262,14 +262,14 @@ void PEI::saveCalleeSavedRegisters(MachineFunction &Fn) {
|
||||
// Add code to restore the callee-save registers in each exiting block.
|
||||
for (MachineFunction::iterator FI = Fn.begin(), E = Fn.end(); FI != E; ++FI)
|
||||
// If last instruction is a return instruction, add an epilogue.
|
||||
if (!FI->empty() && FI->back().getDesc()->isReturn()) {
|
||||
if (!FI->empty() && FI->back().getDesc().isReturn()) {
|
||||
MBB = FI;
|
||||
I = MBB->end(); --I;
|
||||
|
||||
// Skip over all terminator instructions, which are part of the return
|
||||
// sequence.
|
||||
MachineBasicBlock::iterator I2 = I;
|
||||
while (I2 != MBB->begin() && (--I2)->getDesc()->isTerminator())
|
||||
while (I2 != MBB->begin() && (--I2)->getDesc().isTerminator())
|
||||
I = I2;
|
||||
|
||||
bool AtStart = I == MBB->begin();
|
||||
@ -485,7 +485,7 @@ void PEI::insertPrologEpilogCode(MachineFunction &Fn) {
|
||||
// Add epilogue to restore the callee-save registers in each exiting block
|
||||
for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
|
||||
// If last instruction is a return instruction, add an epilogue
|
||||
if (!I->empty() && I->back().getDesc()->isReturn())
|
||||
if (!I->empty() && I->back().getDesc().isReturn())
|
||||
Fn.getTarget().getRegisterInfo()->emitEpilogue(Fn, *I);
|
||||
}
|
||||
}
|
||||
|
@ -649,7 +649,7 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
|
||||
while (MII != MBB.end()) {
|
||||
MachineInstr *MI = MII++;
|
||||
MBBCurTime++;
|
||||
const TargetInstrDescriptor &TID = TII.get(MI->getOpcode());
|
||||
const TargetInstrDesc &TID = MI->getDesc();
|
||||
DEBUG(DOUT << "\nTime=" << MBBCurTime << " Starting RegAlloc of: " << *MI;
|
||||
DOUT << " Regs have values: ";
|
||||
for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i)
|
||||
@ -750,8 +750,8 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
|
||||
}
|
||||
|
||||
// Loop over the implicit defs, spilling them as well.
|
||||
if (TID.ImplicitDefs) {
|
||||
for (const unsigned *ImplicitDefs = TID.ImplicitDefs;
|
||||
if (TID.getImplicitDefs()) {
|
||||
for (const unsigned *ImplicitDefs = TID.getImplicitDefs();
|
||||
*ImplicitDefs; ++ImplicitDefs) {
|
||||
unsigned Reg = *ImplicitDefs;
|
||||
if (PhysRegsUsed[Reg] != -2) {
|
||||
|
@ -563,7 +563,7 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
|
||||
// Otherwise, sequentially allocate each instruction in the MBB.
|
||||
while (MII != MBB.end()) {
|
||||
MachineInstr *MI = MII++;
|
||||
const TargetInstrDescriptor &TID = TII.get(MI->getOpcode());
|
||||
const TargetInstrDesc &TID = MI->getDesc();
|
||||
DEBUG(DOUT << "\nStarting RegAlloc of: " << *MI;
|
||||
DOUT << " Regs have values: ";
|
||||
for (unsigned i = 0; i != MRI->getNumRegs(); ++i)
|
||||
|
@ -173,7 +173,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
|
||||
|
||||
// This is a preliminary pass that will invalidate any registers that are
|
||||
// used by the instruction (including implicit uses).
|
||||
const TargetInstrDescriptor &Desc = *MI->getDesc();
|
||||
const TargetInstrDesc &Desc = MI->getDesc();
|
||||
const unsigned *Regs;
|
||||
if (Desc.ImplicitUses) {
|
||||
for (Regs = Desc.ImplicitUses; *Regs; ++Regs)
|
||||
@ -203,7 +203,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
|
||||
unsigned physReg = Virt2PhysRegMap[virtualReg];
|
||||
if (physReg == 0) {
|
||||
if (op.isDef()) {
|
||||
int TiedOp = MI->getDesc()->findTiedToSrcOperand(i);
|
||||
int TiedOp = Desc.findTiedToSrcOperand(i);
|
||||
if (TiedOp == -1) {
|
||||
physReg = getFreeReg(virtualReg);
|
||||
} else {
|
||||
|
@ -92,10 +92,11 @@ void RegScavenger::forward() {
|
||||
}
|
||||
|
||||
MachineInstr *MI = MBBI;
|
||||
const TargetInstrDesc &TID = MI->getDesc();
|
||||
|
||||
// Reaching a terminator instruction. Restore a scavenged register (which
|
||||
// must be life out.
|
||||
if (MI->getDesc()->isTerminator())
|
||||
if (TID.isTerminator())
|
||||
restoreScavengedReg();
|
||||
|
||||
// Process uses first.
|
||||
@ -122,7 +123,6 @@ void RegScavenger::forward() {
|
||||
setUnused(ChangedRegs);
|
||||
|
||||
// Process defs.
|
||||
const TargetInstrDescriptor *TID = MI->getDesc();
|
||||
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
||||
const MachineOperand &MO = MI->getOperand(i);
|
||||
if (!MO.isRegister() || !MO.isDef())
|
||||
@ -134,7 +134,7 @@ void RegScavenger::forward() {
|
||||
continue;
|
||||
}
|
||||
// Skip two-address destination operand.
|
||||
if (TID->findTiedToSrcOperand(i) != -1) {
|
||||
if (TID.findTiedToSrcOperand(i) != -1) {
|
||||
assert(isUsed(Reg) && "Using an undefined register!");
|
||||
continue;
|
||||
}
|
||||
@ -152,13 +152,13 @@ void RegScavenger::backward() {
|
||||
|
||||
MachineInstr *MI = MBBI;
|
||||
// Process defs first.
|
||||
const TargetInstrDescriptor *TID = MI->getDesc();
|
||||
const TargetInstrDesc &TID = MI->getDesc();
|
||||
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
||||
const MachineOperand &MO = MI->getOperand(i);
|
||||
if (!MO.isRegister() || !MO.isDef())
|
||||
continue;
|
||||
// Skip two-address destination operand.
|
||||
if (TID->findTiedToSrcOperand(i) != -1)
|
||||
if (TID.findTiedToSrcOperand(i) != -1)
|
||||
continue;
|
||||
unsigned Reg = MO.getReg();
|
||||
assert(isUsed(Reg));
|
||||
|
@ -51,7 +51,7 @@ static void CheckForPhysRegDependency(SDNode *Def, SDNode *Use, unsigned Op,
|
||||
|
||||
unsigned ResNo = Use->getOperand(2).ResNo;
|
||||
if (Def->isTargetOpcode()) {
|
||||
const TargetInstrDescriptor &II = TII->get(Def->getTargetOpcode());
|
||||
const TargetInstrDesc &II = TII->get(Def->getTargetOpcode());
|
||||
if (ResNo >= II.getNumDefs() &&
|
||||
II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
|
||||
PhysReg = Reg;
|
||||
@ -148,7 +148,7 @@ void ScheduleDAG::BuildSchedUnits() {
|
||||
|
||||
if (MainNode->isTargetOpcode()) {
|
||||
unsigned Opc = MainNode->getTargetOpcode();
|
||||
const TargetInstrDescriptor &TID = TII->get(Opc);
|
||||
const TargetInstrDesc &TID = TII->get(Opc);
|
||||
for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
|
||||
if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
|
||||
SU->isTwoAddress = true;
|
||||
@ -291,15 +291,15 @@ unsigned ScheduleDAG::CountOperands(SDNode *Node) {
|
||||
static const TargetRegisterClass *getInstrOperandRegClass(
|
||||
const MRegisterInfo *MRI,
|
||||
const TargetInstrInfo *TII,
|
||||
const TargetInstrDescriptor *II,
|
||||
const TargetInstrDesc &II,
|
||||
unsigned Op) {
|
||||
if (Op >= II->getNumOperands()) {
|
||||
assert(II->isVariadic() && "Invalid operand # of instruction");
|
||||
if (Op >= II.getNumOperands()) {
|
||||
assert(II.isVariadic() && "Invalid operand # of instruction");
|
||||
return NULL;
|
||||
}
|
||||
if (II->OpInfo[Op].isLookupPtrRegClass())
|
||||
if (II.OpInfo[Op].isLookupPtrRegClass())
|
||||
return TII->getPointerRegClass();
|
||||
return MRI->getRegClass(II->OpInfo[Op].RegClass);
|
||||
return MRI->getRegClass(II.OpInfo[Op].RegClass);
|
||||
}
|
||||
|
||||
void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
|
||||
@ -371,7 +371,7 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
|
||||
|
||||
void ScheduleDAG::CreateVirtualRegisters(SDNode *Node,
|
||||
MachineInstr *MI,
|
||||
const TargetInstrDescriptor &II,
|
||||
const TargetInstrDesc &II,
|
||||
DenseMap<SDOperand, unsigned> &VRBaseMap) {
|
||||
for (unsigned i = 0; i < II.getNumDefs(); ++i) {
|
||||
// If the specific node value is only used by a CopyToReg and the dest reg
|
||||
@ -396,7 +396,7 @@ void ScheduleDAG::CreateVirtualRegisters(SDNode *Node,
|
||||
// Create the result registers for this node and add the result regs to
|
||||
// the machine instruction.
|
||||
if (VRBase == 0) {
|
||||
const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i);
|
||||
const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, II, i);
|
||||
assert(RC && "Isn't a register operand!");
|
||||
VRBase = RegInfo.createVirtualRegister(RC);
|
||||
MI->addOperand(MachineOperand::CreateReg(VRBase, true));
|
||||
@ -422,7 +422,7 @@ static unsigned getVR(SDOperand Op, DenseMap<SDOperand, unsigned> &VRBaseMap) {
|
||||
/// assertions only.
|
||||
void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
|
||||
unsigned IIOpNum,
|
||||
const TargetInstrDescriptor *II,
|
||||
const TargetInstrDesc *II,
|
||||
DenseMap<SDOperand, unsigned> &VRBaseMap) {
|
||||
if (Op.isTargetOpcode()) {
|
||||
// Note that this case is redundant with the final else block, but we
|
||||
@ -434,16 +434,16 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
|
||||
|
||||
// Get/emit the operand.
|
||||
unsigned VReg = getVR(Op, VRBaseMap);
|
||||
const TargetInstrDescriptor *TID = MI->getDesc();
|
||||
bool isOptDef = (IIOpNum < TID->getNumOperands())
|
||||
? (TID->OpInfo[IIOpNum].isOptionalDef()) : false;
|
||||
const TargetInstrDesc &TID = MI->getDesc();
|
||||
bool isOptDef = (IIOpNum < TID.getNumOperands())
|
||||
? (TID.OpInfo[IIOpNum].isOptionalDef()) : false;
|
||||
MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
|
||||
|
||||
// Verify that it is right.
|
||||
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
|
||||
if (II) {
|
||||
const TargetRegisterClass *RC =
|
||||
getInstrOperandRegClass(MRI, TII, II, IIOpNum);
|
||||
getInstrOperandRegClass(MRI, TII, *II, IIOpNum);
|
||||
assert(RC && "Don't have operand info for this instruction!");
|
||||
const TargetRegisterClass *VRC = RegInfo.getRegClass(VReg);
|
||||
if (VRC != RC) {
|
||||
@ -507,7 +507,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
|
||||
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
|
||||
if (II) {
|
||||
const TargetRegisterClass *RC =
|
||||
getInstrOperandRegClass(MRI, TII, II, IIOpNum);
|
||||
getInstrOperandRegClass(MRI, TII, *II, IIOpNum);
|
||||
assert(RC && "Don't have operand info for this instruction!");
|
||||
assert(RegInfo.getRegClass(VReg) == RC &&
|
||||
"Register class of operand and regclass of use don't agree!");
|
||||
@ -669,7 +669,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo,
|
||||
return;
|
||||
}
|
||||
|
||||
const TargetInstrDescriptor &II = TII->get(Opc);
|
||||
const TargetInstrDesc &II = TII->get(Opc);
|
||||
|
||||
unsigned NumResults = CountResults(Node);
|
||||
unsigned NodeOperands = CountOperands(Node);
|
||||
|
@ -148,7 +148,7 @@ void ScheduleDAGRRList::CommuteNodesToReducePressure() {
|
||||
if (!SU || !SU->Node) continue;
|
||||
if (SU->isCommutable) {
|
||||
unsigned Opc = SU->Node->getTargetOpcode();
|
||||
const TargetInstrDescriptor &TID = TII->get(Opc);
|
||||
const TargetInstrDesc &TID = TII->get(Opc);
|
||||
unsigned NumRes = TID.getNumDefs();
|
||||
unsigned NumOps = CountOperands(SU->Node);
|
||||
for (unsigned j = 0; j != NumOps; ++j) {
|
||||
@ -431,7 +431,7 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
|
||||
|
||||
SUnit *NewSU = NewSUnit(N);
|
||||
SUnitMap[N].push_back(NewSU);
|
||||
const TargetInstrDescriptor &TID = TII->get(N->getTargetOpcode());
|
||||
const TargetInstrDesc &TID = TII->get(N->getTargetOpcode());
|
||||
for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
|
||||
if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
|
||||
NewSU->isTwoAddress = true;
|
||||
@ -622,7 +622,7 @@ void ScheduleDAGRRList::InsertCCCopiesAndMoveSuccs(SUnit *SU, unsigned Reg,
|
||||
/// FIXME: Move to SelectionDAG?
|
||||
static MVT::ValueType getPhysicalRegisterVT(SDNode *N, unsigned Reg,
|
||||
const TargetInstrInfo *TII) {
|
||||
const TargetInstrDescriptor &TID = TII->get(N->getTargetOpcode());
|
||||
const TargetInstrDesc &TID = TII->get(N->getTargetOpcode());
|
||||
assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!");
|
||||
unsigned NumRes = TID.getNumDefs();
|
||||
for (const unsigned *ImpDef = TID.getImplicitDefs(); *ImpDef; ++ImpDef) {
|
||||
@ -665,7 +665,7 @@ bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU,
|
||||
SDNode *Node = (i == 0) ? SU->Node : SU->FlaggedNodes[i-1];
|
||||
if (!Node || !Node->isTargetOpcode())
|
||||
continue;
|
||||
const TargetInstrDescriptor &TID = TII->get(Node->getTargetOpcode());
|
||||
const TargetInstrDesc &TID = TII->get(Node->getTargetOpcode());
|
||||
if (!TID.ImplicitDefs)
|
||||
continue;
|
||||
for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg) {
|
||||
@ -1288,7 +1288,7 @@ template<class SF>
|
||||
bool BURegReductionPriorityQueue<SF>::canClobber(SUnit *SU, SUnit *Op) {
|
||||
if (SU->isTwoAddress) {
|
||||
unsigned Opc = SU->Node->getTargetOpcode();
|
||||
const TargetInstrDescriptor &TID = TII->get(Opc);
|
||||
const TargetInstrDesc &TID = TII->get(Opc);
|
||||
unsigned NumRes = TID.getNumDefs();
|
||||
unsigned NumOps = ScheduleDAG::CountOperands(SU->Node);
|
||||
for (unsigned i = 0; i != NumOps; ++i) {
|
||||
@ -1364,7 +1364,7 @@ void BURegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() {
|
||||
continue;
|
||||
|
||||
unsigned Opc = Node->getTargetOpcode();
|
||||
const TargetInstrDescriptor &TID = TII->get(Opc);
|
||||
const TargetInstrDesc &TID = TII->get(Opc);
|
||||
unsigned NumRes = TID.getNumDefs();
|
||||
unsigned NumOps = ScheduleDAG::CountOperands(Node);
|
||||
for (unsigned j = 0; j != NumOps; ++j) {
|
||||
|
@ -35,23 +35,24 @@ MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI) const {
|
||||
bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
|
||||
const std::vector<MachineOperand> &Pred) const {
|
||||
bool MadeChange = false;
|
||||
const TargetInstrDescriptor *TID = MI->getDesc();
|
||||
if (TID->isPredicable()) {
|
||||
for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
||||
if (TID->OpInfo[i].isPredicate()) {
|
||||
MachineOperand &MO = MI->getOperand(i);
|
||||
if (MO.isReg()) {
|
||||
MO.setReg(Pred[j].getReg());
|
||||
MadeChange = true;
|
||||
} else if (MO.isImm()) {
|
||||
MO.setImm(Pred[j].getImm());
|
||||
MadeChange = true;
|
||||
} else if (MO.isMBB()) {
|
||||
MO.setMBB(Pred[j].getMBB());
|
||||
MadeChange = true;
|
||||
}
|
||||
++j;
|
||||
const TargetInstrDesc &TID = MI->getDesc();
|
||||
if (!TID.isPredicable())
|
||||
return false;
|
||||
|
||||
for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
||||
if (TID.OpInfo[i].isPredicate()) {
|
||||
MachineOperand &MO = MI->getOperand(i);
|
||||
if (MO.isReg()) {
|
||||
MO.setReg(Pred[j].getReg());
|
||||
MadeChange = true;
|
||||
} else if (MO.isImm()) {
|
||||
MO.setImm(Pred[j].getImm());
|
||||
MadeChange = true;
|
||||
} else if (MO.isMBB()) {
|
||||
MO.setMBB(Pred[j].getMBB());
|
||||
MadeChange = true;
|
||||
}
|
||||
++j;
|
||||
}
|
||||
}
|
||||
return MadeChange;
|
||||
|
@ -93,11 +93,11 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
|
||||
mbbi != mbbe; ++mbbi) {
|
||||
for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
|
||||
mi != me; ++mi) {
|
||||
const TargetInstrDescriptor *TID = mi->getDesc();
|
||||
const TargetInstrDesc &TID = mi->getDesc();
|
||||
|
||||
bool FirstTied = true;
|
||||
for (unsigned si = 1, e = TID->getNumOperands(); si < e; ++si) {
|
||||
int ti = TID->getOperandConstraint(si, TOI::TIED_TO);
|
||||
for (unsigned si = 1, e = TID.getNumOperands(); si < e; ++si) {
|
||||
int ti = TID.getOperandConstraint(si, TOI::TIED_TO);
|
||||
if (ti == -1)
|
||||
continue;
|
||||
|
||||
@ -144,7 +144,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
|
||||
// so, swap the B and C operands. This makes the live ranges of A
|
||||
// and C joinable.
|
||||
// FIXME: This code also works for A := B op C instructions.
|
||||
if (TID->isCommutable() && mi->getNumOperands() >= 3) {
|
||||
if (TID.isCommutable() && mi->getNumOperands() >= 3) {
|
||||
assert(mi->getOperand(3-si).isRegister() &&
|
||||
"Not a proper commutative instruction!");
|
||||
unsigned regC = mi->getOperand(3-si).getReg();
|
||||
@ -172,12 +172,12 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
|
||||
|
||||
// If this instruction is potentially convertible to a true
|
||||
// three-address instruction,
|
||||
if (TID->isConvertibleTo3Addr()) {
|
||||
if (TID.isConvertibleTo3Addr()) {
|
||||
// FIXME: This assumes there are no more operands which are tied
|
||||
// to another register.
|
||||
#ifndef NDEBUG
|
||||
for (unsigned i = si+1, e = TID->getNumOperands(); i < e; ++i)
|
||||
assert(TID->getOperandConstraint(i, TOI::TIED_TO) == -1);
|
||||
for (unsigned i = si+1, e = TID.getNumOperands(); i < e; ++i)
|
||||
assert(TID.getOperandConstraint(i, TOI::TIED_TO) == -1);
|
||||
#endif
|
||||
|
||||
if (MachineInstr *New = TII.convertToThreeAddress(mbbi, mi, LV)) {
|
||||
|
@ -537,7 +537,7 @@ static bool InvalidateRegDef(MachineBasicBlock::iterator I,
|
||||
/// over.
|
||||
static void UpdateKills(MachineInstr &MI, BitVector &RegKills,
|
||||
std::vector<MachineOperand*> &KillOps) {
|
||||
const TargetInstrDescriptor *TID = MI.getDesc();
|
||||
const TargetInstrDesc &TID = MI.getDesc();
|
||||
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
|
||||
MachineOperand &MO = MI.getOperand(i);
|
||||
if (!MO.isRegister() || !MO.isUse())
|
||||
@ -552,8 +552,8 @@ static void UpdateKills(MachineInstr &MI, BitVector &RegKills,
|
||||
KillOps[Reg]->setIsKill(false);
|
||||
KillOps[Reg] = NULL;
|
||||
RegKills.reset(Reg);
|
||||
if (i < TID->getNumOperands() &&
|
||||
TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
|
||||
if (i < TID.getNumOperands() &&
|
||||
TID.getOperandConstraint(i, TOI::TIED_TO) == -1)
|
||||
// Unless it's a two-address operand, this is the new kill.
|
||||
MO.setIsKill();
|
||||
}
|
||||
@ -966,7 +966,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
|
||||
NextMII = next(MII);
|
||||
|
||||
MachineInstr &MI = *MII;
|
||||
const TargetInstrDescriptor *TID = MI.getDesc();
|
||||
const TargetInstrDesc &TID = MI.getDesc();
|
||||
|
||||
// Insert restores here if asked to.
|
||||
if (VRM.isRestorePt(&MI)) {
|
||||
@ -1082,7 +1082,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
|
||||
// aren't allowed to modify the reused register. If none of these cases
|
||||
// apply, reuse it.
|
||||
bool CanReuse = true;
|
||||
int ti = TID->getOperandConstraint(i, TOI::TIED_TO);
|
||||
int ti = TID.getOperandConstraint(i, TOI::TIED_TO);
|
||||
if (ti != -1 &&
|
||||
MI.getOperand(ti).isRegister() &&
|
||||
MI.getOperand(ti).getReg() == VirtReg) {
|
||||
@ -1234,7 +1234,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
|
||||
Spills.addAvailable(SSorRMId, &MI, PhysReg);
|
||||
// Assumes this is the last use. IsKill will be unset if reg is reused
|
||||
// unless it's a two-address operand.
|
||||
if (TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
|
||||
if (TID.getOperandConstraint(i, TOI::TIED_TO) == -1)
|
||||
MI.getOperand(i).setIsKill();
|
||||
unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg;
|
||||
MI.getOperand(i).setReg(RReg);
|
||||
@ -1436,7 +1436,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
|
||||
// If this def is part of a two-address operand, make sure to execute
|
||||
// the store from the correct physical register.
|
||||
unsigned PhysReg;
|
||||
int TiedOp = MI.getDesc()->findTiedToSrcOperand(i);
|
||||
int TiedOp = MI.getDesc().findTiedToSrcOperand(i);
|
||||
if (TiedOp != -1) {
|
||||
PhysReg = MI.getOperand(TiedOp).getReg();
|
||||
if (SubIdx) {
|
||||
|
@ -55,7 +55,7 @@ namespace {
|
||||
|
||||
void emitInstruction(const MachineInstr &MI);
|
||||
int getMachineOpValue(const MachineInstr &MI, unsigned OpIndex);
|
||||
unsigned getBaseOpcodeFor(const TargetInstrDescriptor *TID);
|
||||
unsigned getBaseOpcodeFor(const TargetInstrDesc &TID);
|
||||
unsigned getBinaryCodeForInstr(const MachineInstr &MI);
|
||||
|
||||
void emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub);
|
||||
@ -103,8 +103,8 @@ bool Emitter::runOnMachineFunction(MachineFunction &MF) {
|
||||
}
|
||||
|
||||
/// getBaseOpcodeFor - Return the opcode value
|
||||
unsigned Emitter::getBaseOpcodeFor(const TargetInstrDescriptor *TID) {
|
||||
return (TID->TSFlags & ARMII::OpcodeMask) >> ARMII::OpcodeShift;
|
||||
unsigned Emitter::getBaseOpcodeFor(const TargetInstrDesc &TID) {
|
||||
return (TID.TSFlags & ARMII::OpcodeMask) >> ARMII::OpcodeShift;
|
||||
}
|
||||
|
||||
/// getShiftOp - Verify which is the shift opcode (bit[6:5]) of the
|
||||
@ -201,15 +201,15 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
|
||||
}
|
||||
|
||||
unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
|
||||
const TargetInstrDescriptor *Desc = MI.getDesc();
|
||||
unsigned opcode = Desc->Opcode;
|
||||
const TargetInstrDesc &Desc = MI.getDesc();
|
||||
unsigned opcode = Desc.Opcode;
|
||||
// initial instruction mask
|
||||
unsigned Value = 0xE0000000;
|
||||
unsigned op;
|
||||
|
||||
switch (Desc->TSFlags & ARMII::AddrModeMask) {
|
||||
switch (Desc.TSFlags & ARMII::AddrModeMask) {
|
||||
case ARMII::AddrModeNone: {
|
||||
switch(Desc->TSFlags & ARMII::FormMask) {
|
||||
switch(Desc.TSFlags & ARMII::FormMask) {
|
||||
default: {
|
||||
assert(0 && "Unknown instruction subtype!");
|
||||
// treat special instruction CLZ
|
||||
@ -241,7 +241,7 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
|
||||
unsigned char BaseOpcode = getBaseOpcodeFor(Desc);
|
||||
Value |= BaseOpcode << 4;
|
||||
|
||||
unsigned Format = (Desc->TSFlags & ARMII::FormMask);
|
||||
unsigned Format = (Desc.TSFlags & ARMII::FormMask);
|
||||
if (Format == ARMII::MulSMUL)
|
||||
Value |= 1 << 22;
|
||||
|
||||
@ -342,7 +342,7 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
|
||||
|
||||
// treat 3 special instructions: MOVsra_flag, MOVsrl_flag and
|
||||
// MOVrx.
|
||||
unsigned Format = (Desc->TSFlags & ARMII::FormMask);
|
||||
unsigned Format = Desc.TSFlags & ARMII::FormMask;
|
||||
if (Format == ARMII::DPRdMisc) {
|
||||
Value |= getMachineOpValue(MI,0) << ARMII::RegRdShift;
|
||||
Value |= getMachineOpValue(MI,1);
|
||||
@ -499,7 +499,7 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
|
||||
// bit 26 is always 1
|
||||
Value |= 1 << 26;
|
||||
|
||||
unsigned Index = (Desc->TSFlags & ARMII::IndexModeMask);
|
||||
unsigned Index = Desc.TSFlags & ARMII::IndexModeMask;
|
||||
// if the instruction uses offset addressing or pre-indexed addressing,
|
||||
// set bit P(24) to 1
|
||||
if (Index == ARMII::IndexModePre || Index == 0)
|
||||
@ -508,7 +508,7 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
|
||||
if (Index == ARMII::IndexModePre)
|
||||
Value |= 1 << 21;
|
||||
|
||||
unsigned Format = (Desc->TSFlags & ARMII::FormMask);
|
||||
unsigned Format = Desc.TSFlags & ARMII::FormMask;
|
||||
// If it is a load instruction (except LDRD), set bit L(20) to 1
|
||||
if (Format == ARMII::LdFrm)
|
||||
Value |= 1 << ARMII::L_BitShift;
|
||||
@ -555,14 +555,13 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
|
||||
break;
|
||||
}
|
||||
case ARMII::AddrMode3: {
|
||||
|
||||
unsigned Index = (Desc->TSFlags & ARMII::IndexModeMask);
|
||||
unsigned Index = Desc.TSFlags & ARMII::IndexModeMask;
|
||||
// if the instruction uses offset addressing or pre-indexed addressing,
|
||||
// set bit P(24) to 1
|
||||
if (Index == ARMII::IndexModePre || Index == 0)
|
||||
Value |= 1 << ARMII::IndexShift;
|
||||
|
||||
unsigned Format = (Desc->TSFlags & ARMII::FormMask);
|
||||
unsigned Format = Desc.TSFlags & ARMII::FormMask;
|
||||
// If it is a load instruction (except LDRD), set bit L(20) to 1
|
||||
if (Format == ARMII::LdFrm && opcode != ARM::LDRD)
|
||||
Value |= 1 << ARMII::L_BitShift;
|
||||
@ -607,7 +606,7 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
|
||||
// bit 27 is always 1
|
||||
Value |= 1 << 27;
|
||||
|
||||
unsigned Format = (Desc->TSFlags & ARMII::FormMask);
|
||||
unsigned Format = Desc.TSFlags & ARMII::FormMask;
|
||||
// if it is a load instr, set bit L(20) to 1
|
||||
if (Format == ARMII::LdFrm)
|
||||
Value |= 1 << ARMII::L_BitShift;
|
||||
|
@ -371,7 +371,7 @@ void ARMConstantIslands::InitialFunctionScan(MachineFunction &Fn,
|
||||
MBBSize += ARM::GetInstSize(I);
|
||||
|
||||
int Opc = I->getOpcode();
|
||||
if (I->getDesc()->isBranch()) {
|
||||
if (I->getDesc().isBranch()) {
|
||||
bool isCond = false;
|
||||
unsigned Bits = 0;
|
||||
unsigned Scale = 1;
|
||||
@ -423,7 +423,7 @@ void ARMConstantIslands::InitialFunctionScan(MachineFunction &Fn,
|
||||
// Basic size info comes from the TSFlags field.
|
||||
unsigned Bits = 0;
|
||||
unsigned Scale = 1;
|
||||
unsigned TSFlags = I->getDesc()->TSFlags;
|
||||
unsigned TSFlags = I->getDesc().TSFlags;
|
||||
switch (TSFlags & ARMII::AddrModeMask) {
|
||||
default:
|
||||
// Constant pool entries can reach anything.
|
||||
|
@ -63,7 +63,7 @@ bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
|
||||
return true;
|
||||
case ARM::MOVr:
|
||||
case ARM::tMOVr:
|
||||
assert(MI.getDesc()->getNumOperands() >= 2 &&
|
||||
assert(MI.getDesc().getNumOperands() >= 2 &&
|
||||
MI.getOperand(0).isRegister() &&
|
||||
MI.getOperand(1).isRegister() &&
|
||||
"Invalid ARM MOV instruction");
|
||||
@ -180,7 +180,7 @@ ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
|
||||
return NULL;
|
||||
|
||||
MachineInstr *MI = MBBI;
|
||||
unsigned TSFlags = MI->getDesc()->TSFlags;
|
||||
unsigned TSFlags = MI->getDesc().TSFlags;
|
||||
bool isPre = false;
|
||||
switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
|
||||
default: return NULL;
|
||||
@ -200,9 +200,9 @@ ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
|
||||
MachineInstr *UpdateMI = NULL;
|
||||
MachineInstr *MemMI = NULL;
|
||||
unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
|
||||
const TargetInstrDescriptor *TID = MI->getDesc();
|
||||
unsigned NumOps = TID->getNumOperands();
|
||||
bool isLoad = TID->isSimpleLoad();
|
||||
const TargetInstrDesc &TID = MI->getDesc();
|
||||
unsigned NumOps = TID.getNumOperands();
|
||||
bool isLoad = TID.isSimpleLoad();
|
||||
const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
|
||||
const MachineOperand &Base = MI->getOperand(2);
|
||||
const MachineOperand &Offset = MI->getOperand(NumOps-3);
|
||||
@ -837,8 +837,8 @@ ARMInstrInfo::SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
|
||||
|
||||
bool ARMInstrInfo::DefinesPredicate(MachineInstr *MI,
|
||||
std::vector<MachineOperand> &Pred) const {
|
||||
const TargetInstrDescriptor *TID = MI->getDesc();
|
||||
if (!TID->getImplicitDefs() && !TID->hasOptionalDef())
|
||||
const TargetInstrDesc &TID = MI->getDesc();
|
||||
if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
|
||||
return false;
|
||||
|
||||
bool Found = false;
|
||||
@ -870,8 +870,8 @@ unsigned ARM::GetInstSize(MachineInstr *MI) {
|
||||
const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
|
||||
|
||||
// Basic size info comes from the TSFlags field.
|
||||
const TargetInstrDescriptor *TID = MI->getDesc();
|
||||
unsigned TSFlags = TID->TSFlags;
|
||||
const TargetInstrDesc &TID = MI->getDesc();
|
||||
unsigned TSFlags = TID.TSFlags;
|
||||
|
||||
switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
|
||||
default:
|
||||
@ -897,9 +897,9 @@ unsigned ARM::GetInstSize(MachineInstr *MI) {
|
||||
case ARM::tBR_JTr: {
|
||||
// These are jumptable branches, i.e. a branch followed by an inlined
|
||||
// jumptable. The size is 4 + 4 * number of entries.
|
||||
unsigned NumOps = TID->getNumOperands();
|
||||
unsigned NumOps = TID.getNumOperands();
|
||||
MachineOperand JTOP =
|
||||
MI->getOperand(NumOps - (TID->isPredicable() ? 3 : 2));
|
||||
MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
|
||||
unsigned JTI = JTOP.getIndex();
|
||||
MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
|
||||
const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
|
||||
|
@ -599,8 +599,8 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
|
||||
unsigned Base = MBBI->getOperand(1).getReg();
|
||||
unsigned PredReg = 0;
|
||||
ARMCC::CondCodes Pred = getInstrPredicate(MBBI, PredReg);
|
||||
const TargetInstrDescriptor *TID = MBBI->getDesc();
|
||||
unsigned OffField = MBBI->getOperand(TID->getNumOperands()-3).getImm();
|
||||
unsigned NumOperands = MBBI->getDesc().getNumOperands();
|
||||
unsigned OffField = MBBI->getOperand(NumOperands-3).getImm();
|
||||
int Offset = isAM2
|
||||
? ARM_AM::getAM2Offset(OffField) : ARM_AM::getAM5Offset(OffField) * 4;
|
||||
if (isAM2) {
|
||||
|
@ -581,7 +581,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
}
|
||||
|
||||
unsigned Opcode = MI.getOpcode();
|
||||
const TargetInstrDescriptor &Desc = *MI.getDesc();
|
||||
const TargetInstrDesc &Desc = MI.getDesc();
|
||||
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
|
||||
bool isSub = false;
|
||||
|
||||
@ -1036,7 +1036,7 @@ ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
|
||||
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
|
||||
if (I->getOperand(i).isFrameIndex()) {
|
||||
unsigned Opcode = I->getOpcode();
|
||||
const TargetInstrDescriptor &Desc = TII.get(Opcode);
|
||||
const TargetInstrDesc &Desc = TII.get(Opcode);
|
||||
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
|
||||
if (AddrMode == ARMII::AddrMode3) {
|
||||
Limit = (1 << 8) - 1;
|
||||
|
@ -59,7 +59,7 @@ runOnMachineBasicBlock(MachineBasicBlock &MBB)
|
||||
{
|
||||
bool Changed = false;
|
||||
for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
|
||||
if (I->getDesc()->hasDelaySlot()) {
|
||||
if (I->getDesc().hasDelaySlot()) {
|
||||
MachineBasicBlock::iterator J = I;
|
||||
++J;
|
||||
BuildMI(MBB, J, TII->get(Mips::NOP));
|
||||
|
@ -175,7 +175,7 @@ bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
|
||||
// If there is only one terminator instruction, process it.
|
||||
unsigned LastOpc = LastInst->getOpcode();
|
||||
if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
|
||||
if (!LastInst->getDesc()->isBranch())
|
||||
if (!LastInst->getDesc().isBranch())
|
||||
return true;
|
||||
|
||||
// Unconditional branch
|
||||
@ -259,7 +259,7 @@ InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
} else {
|
||||
// Conditional branch.
|
||||
unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
|
||||
const TargetInstrDescriptor &TID = get(Opc);
|
||||
const TargetInstrDesc &TID = get(Opc);
|
||||
|
||||
if (TID.getNumOperands() == 3)
|
||||
BuildMI(&MBB, TID).addReg(Cond[1].getReg())
|
||||
@ -275,15 +275,13 @@ InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
|
||||
// Two-way Conditional branch.
|
||||
unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
|
||||
const TargetInstrDescriptor &TID = get(Opc);
|
||||
const TargetInstrDesc &TID = get(Opc);
|
||||
|
||||
if (TID.getNumOperands() == 3)
|
||||
BuildMI(&MBB, TID).addReg(Cond[1].getReg())
|
||||
.addReg(Cond[2].getReg())
|
||||
BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
|
||||
.addMBB(TBB);
|
||||
else
|
||||
BuildMI(&MBB, TID).addReg(Cond[1].getReg())
|
||||
.addMBB(TBB);
|
||||
BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addMBB(TBB);
|
||||
|
||||
BuildMI(&MBB, get(Mips::J)).addMBB(FBB);
|
||||
return 2;
|
||||
|
@ -70,7 +70,7 @@ PPCHazardRecognizer970::GetInstrType(unsigned Opcode,
|
||||
}
|
||||
Opcode -= ISD::BUILTIN_OP_END;
|
||||
|
||||
const TargetInstrDescriptor &TID = TII.get(Opcode);
|
||||
const TargetInstrDesc &TID = TII.get(Opcode);
|
||||
|
||||
isLoad = TID.isSimpleLoad();
|
||||
isStore = TID.mayStore();
|
||||
|
@ -262,13 +262,13 @@ void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) {
|
||||
|
||||
// Find all return blocks, outputting a restore in each epilog.
|
||||
for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
|
||||
if (!BB->empty() && BB->back().getDesc()->isReturn()) {
|
||||
if (!BB->empty() && BB->back().getDesc().isReturn()) {
|
||||
IP = BB->end(); --IP;
|
||||
|
||||
// Skip over all terminator instructions, which are part of the return
|
||||
// sequence.
|
||||
MachineBasicBlock::iterator I2 = IP;
|
||||
while (I2 != BB->begin() && (--I2)->getDesc()->isTerminator())
|
||||
while (I2 != BB->begin() && (--I2)->getDesc().isTerminator())
|
||||
IP = I2;
|
||||
|
||||
// Emit: MTVRSAVE InVRSave
|
||||
|
@ -540,7 +540,7 @@ static void RemoveVRSaveCode(MachineInstr *MI) {
|
||||
// epilog blocks.
|
||||
for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
|
||||
// If last instruction is a return instruction, add an epilogue
|
||||
if (!I->empty() && I->back().getDesc()->isReturn()) {
|
||||
if (!I->empty() && I->back().getDesc().isReturn()) {
|
||||
bool FoundIt = false;
|
||||
for (MBBI = I->end(); MBBI != I->begin(); ) {
|
||||
--MBBI;
|
||||
|
@ -65,7 +65,7 @@ FunctionPass *llvm::createSparcDelaySlotFillerPass(TargetMachine &tm) {
|
||||
bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
|
||||
bool Changed = false;
|
||||
for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
|
||||
if (I->getDesc()->hasDelaySlot()) {
|
||||
if (I->getDesc().hasDelaySlot()) {
|
||||
MachineBasicBlock::iterator J = I;
|
||||
++J;
|
||||
BuildMI(MBB, J, TII->get(SP::NOP));
|
||||
|
@ -18,7 +18,7 @@ using namespace llvm;
|
||||
|
||||
/// findTiedToSrcOperand - Returns the operand that is tied to the specified
|
||||
/// dest operand. Returns -1 if there isn't one.
|
||||
int TargetInstrDescriptor::findTiedToSrcOperand(unsigned OpNum) const {
|
||||
int TargetInstrDesc::findTiedToSrcOperand(unsigned OpNum) const {
|
||||
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
|
||||
if (i == OpNum)
|
||||
continue;
|
||||
@ -29,22 +29,22 @@ int TargetInstrDescriptor::findTiedToSrcOperand(unsigned OpNum) const {
|
||||
}
|
||||
|
||||
|
||||
TargetInstrInfo::TargetInstrInfo(const TargetInstrDescriptor* Desc,
|
||||
TargetInstrInfo::TargetInstrInfo(const TargetInstrDesc* Desc,
|
||||
unsigned numOpcodes)
|
||||
: desc(Desc), NumOpcodes(numOpcodes) {
|
||||
: Descriptors(Desc), NumOpcodes(numOpcodes) {
|
||||
}
|
||||
|
||||
TargetInstrInfo::~TargetInstrInfo() {
|
||||
}
|
||||
|
||||
bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
|
||||
const TargetInstrDescriptor *TID = MI->getDesc();
|
||||
if (!TID->isTerminator()) return false;
|
||||
const TargetInstrDesc &TID = MI->getDesc();
|
||||
if (!TID.isTerminator()) return false;
|
||||
|
||||
// Conditional branch is a special case.
|
||||
if (TID->isBranch() && !TID->isBarrier())
|
||||
if (TID.isBranch() && !TID.isBarrier())
|
||||
return true;
|
||||
if (!TID->isPredicable())
|
||||
if (!TID.isPredicable())
|
||||
return true;
|
||||
return !isPredicated(MI);
|
||||
}
|
||||
|
@ -60,7 +60,7 @@ namespace {
|
||||
}
|
||||
|
||||
void emitInstruction(const MachineInstr &MI,
|
||||
const TargetInstrDescriptor *Desc);
|
||||
const TargetInstrDesc *Desc);
|
||||
|
||||
private:
|
||||
void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
|
||||
@ -115,10 +115,10 @@ bool Emitter::runOnMachineFunction(MachineFunction &MF) {
|
||||
MCE.StartMachineBasicBlock(MBB);
|
||||
for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
|
||||
I != E; ++I) {
|
||||
const TargetInstrDescriptor *Desc = I->getDesc();
|
||||
emitInstruction(*I, Desc);
|
||||
const TargetInstrDesc &Desc = I->getDesc();
|
||||
emitInstruction(*I, &Desc);
|
||||
// MOVPC32r is basically a call plus a pop instruction.
|
||||
if (Desc->Opcode == X86::MOVPC32r)
|
||||
if (Desc.getOpcode() == X86::MOVPC32r)
|
||||
emitInstruction(*I, &II->get(X86::POP32r));
|
||||
NumEmitted++; // Keep track of the # of mi's emitted
|
||||
}
|
||||
@ -394,7 +394,7 @@ void Emitter::emitMemModRMByte(const MachineInstr &MI,
|
||||
}
|
||||
}
|
||||
|
||||
static unsigned sizeOfImm(const TargetInstrDescriptor *Desc) {
|
||||
static unsigned sizeOfImm(const TargetInstrDesc *Desc) {
|
||||
switch (Desc->TSFlags & X86II::ImmMask) {
|
||||
case X86II::Imm8: return 1;
|
||||
case X86II::Imm16: return 2;
|
||||
@ -436,18 +436,18 @@ inline static bool isX86_64NonExtLowByteReg(unsigned reg) {
|
||||
/// size, and 3) use of X86-64 extended registers.
|
||||
unsigned Emitter::determineREX(const MachineInstr &MI) {
|
||||
unsigned REX = 0;
|
||||
const TargetInstrDescriptor *Desc = MI.getDesc();
|
||||
const TargetInstrDesc &Desc = MI.getDesc();
|
||||
|
||||
// Pseudo instructions do not need REX prefix byte.
|
||||
if ((Desc->TSFlags & X86II::FormMask) == X86II::Pseudo)
|
||||
if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
|
||||
return 0;
|
||||
if (Desc->TSFlags & X86II::REX_W)
|
||||
if (Desc.TSFlags & X86II::REX_W)
|
||||
REX |= 1 << 3;
|
||||
|
||||
unsigned NumOps = Desc->getNumOperands();
|
||||
unsigned NumOps = Desc.getNumOperands();
|
||||
if (NumOps) {
|
||||
bool isTwoAddr = NumOps > 1 &&
|
||||
Desc->getOperandConstraint(1, TOI::TIED_TO) != -1;
|
||||
Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
|
||||
|
||||
// If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
|
||||
unsigned i = isTwoAddr ? 1 : 0;
|
||||
@ -460,7 +460,7 @@ unsigned Emitter::determineREX(const MachineInstr &MI) {
|
||||
}
|
||||
}
|
||||
|
||||
switch (Desc->TSFlags & X86II::FormMask) {
|
||||
switch (Desc.TSFlags & X86II::FormMask) {
|
||||
case X86II::MRMInitReg:
|
||||
if (isX86_64ExtendedReg(MI.getOperand(0)))
|
||||
REX |= (1 << 0) | (1 << 2);
|
||||
@ -528,7 +528,7 @@ unsigned Emitter::determineREX(const MachineInstr &MI) {
|
||||
}
|
||||
|
||||
void Emitter::emitInstruction(const MachineInstr &MI,
|
||||
const TargetInstrDescriptor *Desc) {
|
||||
const TargetInstrDesc *Desc) {
|
||||
unsigned Opcode = Desc->Opcode;
|
||||
|
||||
// Emit the repeat opcode prefix as needed.
|
||||
|
@ -205,7 +205,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
|
||||
|
||||
for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
|
||||
MachineInstr *MI = I;
|
||||
unsigned Flags = MI->getDesc()->TSFlags;
|
||||
unsigned Flags = MI->getDesc().TSFlags;
|
||||
if ((Flags & X86II::FPTypeMask) == X86II::NotFP)
|
||||
continue; // Efficiently ignore non-fp insts!
|
||||
|
||||
@ -597,7 +597,7 @@ void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
|
||||
///
|
||||
void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
|
||||
MachineInstr *MI = I;
|
||||
unsigned NumOps = MI->getDesc()->getNumOperands();
|
||||
unsigned NumOps = MI->getDesc().getNumOperands();
|
||||
assert((NumOps == 5 || NumOps == 1) &&
|
||||
"Can only handle fst* & ftst instructions!");
|
||||
|
||||
@ -657,7 +657,7 @@ void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
|
||||
///
|
||||
void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
|
||||
MachineInstr *MI = I;
|
||||
unsigned NumOps = MI->getDesc()->getNumOperands();
|
||||
unsigned NumOps = MI->getDesc().getNumOperands();
|
||||
assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
|
||||
|
||||
// Is this the last use of the source register?
|
||||
@ -766,7 +766,7 @@ void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
|
||||
ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
|
||||
MachineInstr *MI = I;
|
||||
|
||||
unsigned NumOperands = MI->getDesc()->getNumOperands();
|
||||
unsigned NumOperands = MI->getDesc().getNumOperands();
|
||||
assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
|
||||
unsigned Dest = getFPReg(MI->getOperand(0));
|
||||
unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
|
||||
@ -864,7 +864,7 @@ void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
|
||||
ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
|
||||
MachineInstr *MI = I;
|
||||
|
||||
unsigned NumOperands = MI->getDesc()->getNumOperands();
|
||||
unsigned NumOperands = MI->getDesc().getNumOperands();
|
||||
assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
|
||||
unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
|
||||
unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
|
||||
|
@ -1243,13 +1243,13 @@ X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
|
||||
}
|
||||
|
||||
bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
|
||||
const TargetInstrDescriptor *TID = MI->getDesc();
|
||||
if (!TID->isTerminator()) return false;
|
||||
const TargetInstrDesc &TID = MI->getDesc();
|
||||
if (!TID.isTerminator()) return false;
|
||||
|
||||
// Conditional branch is a special case.
|
||||
if (TID->isBranch() && !TID->isBarrier())
|
||||
if (TID.isBranch() && !TID.isBarrier())
|
||||
return true;
|
||||
if (!TID->isPredicable())
|
||||
if (!TID.isPredicable())
|
||||
return true;
|
||||
return !isPredicated(MI);
|
||||
}
|
||||
@ -1276,7 +1276,7 @@ bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
|
||||
|
||||
// If there is only one terminator instruction, process it.
|
||||
if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this)) {
|
||||
if (!LastInst->getDesc()->isBranch())
|
||||
if (!LastInst->getDesc().isBranch())
|
||||
return true;
|
||||
|
||||
// If the block ends with a branch there are 3 possibilities:
|
||||
@ -1640,7 +1640,7 @@ static MachineInstr *FuseTwoAddrInst(unsigned Opcode,
|
||||
MIB.addImm(1).addReg(0).addImm(0);
|
||||
|
||||
// Loop over the rest of the ri operands, converting them over.
|
||||
unsigned NumOps = MI->getDesc()->getNumOperands()-2;
|
||||
unsigned NumOps = MI->getDesc().getNumOperands()-2;
|
||||
for (unsigned i = 0; i != NumOps; ++i) {
|
||||
MachineOperand &MO = MI->getOperand(i+2);
|
||||
MIB = X86InstrAddOperand(MIB, MO);
|
||||
@ -1692,9 +1692,9 @@ X86InstrInfo::foldMemoryOperand(MachineInstr *MI, unsigned i,
|
||||
SmallVector<MachineOperand,4> &MOs) const {
|
||||
const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
|
||||
bool isTwoAddrFold = false;
|
||||
unsigned NumOps = MI->getDesc()->getNumOperands();
|
||||
unsigned NumOps = MI->getDesc().getNumOperands();
|
||||
bool isTwoAddr = NumOps > 1 &&
|
||||
MI->getDesc()->getOperandConstraint(1, TOI::TIED_TO) != -1;
|
||||
MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
|
||||
|
||||
MachineInstr *NewMI = NULL;
|
||||
// Folding a memory location into the two-address part of a two-address
|
||||
@ -1798,7 +1798,7 @@ MachineInstr* X86InstrInfo::foldMemoryOperand(MachineInstr *MI,
|
||||
return NULL;
|
||||
|
||||
SmallVector<MachineOperand,4> MOs;
|
||||
unsigned NumOps = LoadMI->getDesc()->getNumOperands();
|
||||
unsigned NumOps = LoadMI->getDesc().getNumOperands();
|
||||
for (unsigned i = NumOps - 4; i != NumOps; ++i)
|
||||
MOs.push_back(LoadMI->getOperand(i));
|
||||
return foldMemoryOperand(MI, Ops[0], MOs);
|
||||
@ -1826,9 +1826,9 @@ bool X86InstrInfo::canFoldMemoryOperand(MachineInstr *MI,
|
||||
|
||||
unsigned OpNum = Ops[0];
|
||||
unsigned Opc = MI->getOpcode();
|
||||
unsigned NumOps = MI->getDesc()->getNumOperands();
|
||||
unsigned NumOps = MI->getDesc().getNumOperands();
|
||||
bool isTwoAddr = NumOps > 1 &&
|
||||
MI->getDesc()->getOperandConstraint(1, TOI::TIED_TO) != -1;
|
||||
MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
|
||||
|
||||
// Folding a memory location into the two-address part of a two-address
|
||||
// instruction is different than folding it other places. It requires
|
||||
@ -1880,7 +1880,7 @@ bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
|
||||
return false;
|
||||
UnfoldStore &= FoldedStore;
|
||||
|
||||
const TargetInstrDescriptor &TID = get(Opc);
|
||||
const TargetInstrDesc &TID = get(Opc);
|
||||
const TargetOperandInfo &TOI = TID.OpInfo[Index];
|
||||
const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
|
||||
? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
|
||||
@ -1979,7 +1979,7 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
|
||||
unsigned Index = I->second.second & 0xf;
|
||||
bool FoldedLoad = I->second.second & (1 << 4);
|
||||
bool FoldedStore = I->second.second & (1 << 5);
|
||||
const TargetInstrDescriptor &TID = get(Opc);
|
||||
const TargetInstrDesc &TID = get(Opc);
|
||||
const TargetOperandInfo &TOI = TID.OpInfo[Index];
|
||||
const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
|
||||
? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
|
||||
|
@ -364,7 +364,7 @@ public:
|
||||
// getBaseOpcodeFor - This function returns the "base" X86 opcode for the
|
||||
// specified machine instruction.
|
||||
//
|
||||
unsigned char getBaseOpcodeFor(const TargetInstrDescriptor *TID) const {
|
||||
unsigned char getBaseOpcodeFor(const TargetInstrDesc *TID) const {
|
||||
return TID->TSFlags >> X86II::OpcodeShift;
|
||||
}
|
||||
unsigned char getBaseOpcodeFor(unsigned Opcode) const {
|
||||
|
@ -729,7 +729,7 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
|
||||
MachineBasicBlock::iterator PI = prior(MBBI);
|
||||
unsigned Opc = PI->getOpcode();
|
||||
if (Opc != X86::POP32r && Opc != X86::POP64r &&
|
||||
!PI->getDesc()->isTerminator())
|
||||
!PI->getDesc().isTerminator())
|
||||
break;
|
||||
--MBBI;
|
||||
}
|
||||
|
@ -261,9 +261,9 @@ void InstrInfoEmitter::run(std::ostream &OS) {
|
||||
// Emit all of the operand info records.
|
||||
EmitOperandInfo(OS, OperandInfoIDs);
|
||||
|
||||
// Emit all of the TargetInstrDescriptor records in their ENUM ordering.
|
||||
// Emit all of the TargetInstrDesc records in their ENUM ordering.
|
||||
//
|
||||
OS << "\nstatic const TargetInstrDescriptor " << TargetName
|
||||
OS << "\nstatic const TargetInstrDesc " << TargetName
|
||||
<< "Insts[] = {\n";
|
||||
std::vector<const CodeGenInstruction*> NumberedInstructions;
|
||||
Target.getInstructionsByEnumValue(NumberedInstructions);
|
||||
|
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Reference in New Issue
Block a user