Hal Finkel 7ca2a7d742 [PowerPC] Add support for dcbtst and icbt (prefetch) ... Adds code generation support for dcbtst (data cache prefetch for write) and icbt (instruction cache prefetch for read - Book E cores only). We still end up with a 'cannot select' error for the non-supported prefetch intrinsic forms. This will be fixed in a later commit. Fixes PR20692. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216339 91177308-0d34-0410-b5e6-96231b3b80d8		2014-08-23 23:21:04 +00:00
..
AArch64	[FastISel][AArch64] Add support for variable shift.	2014-08-21 23:06:07 +00:00
ARM	Revert "ARM: improve RTABI 4.2 conformance on Linux"	2014-08-23 18:29:43 +00:00
CPP
Generic
Hexagon
Inputs
Mips	[mips] Don't use odd-numbered float registers for double arguments for fastcc	2014-08-22 09:23:22 +00:00
MSP430
NVPTX
PowerPC	[PowerPC] Add support for dcbtst and icbt (prefetch)	2014-08-23 23:21:04 +00:00
R600	R600/SI: Use READ2/WRITE2 instructions for 64-bit mem ops with 32-bit alignment	2014-08-22 18:49:35 +00:00
SPARC
SystemZ
Thumb	ARM / x86_64 varargs: Don't save regparms in prologue without va_start	2014-08-22 21:59:26 +00:00
Thumb2	ARM / x86_64 varargs: Don't save regparms in prologue without va_start	2014-08-22 21:59:26 +00:00
X86	[x86] Start fixing a really subtle and terrible form of miscompile in	2014-08-23 10:25:15 +00:00
XCore