Geoff Berry 1a0868d554 [AArch64] Match float round and convert to int instructions. ... Summary: Add patterns for doing floating point round with various rounding modes followed by conversion to int as a single FCVT* instruction. Reviewers: t.p.northover, jmolloy Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D11424 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243422 91177308-0d34-0410-b5e6-96231b3b80d8		2015-07-28 15:24:10 +00:00
..
AArch64	[AArch64] Match float round and convert to int instructions.	2015-07-28 15:24:10 +00:00
AMDGPU	AMDGPU: don't match vgpr loads for constant loads	2015-07-27 18:16:08 +00:00
ARM	DI/Verifier: Fix argument bitrot in DILocalVariable	2015-07-24 23:59:25 +00:00
BPF
CPP
Generic	DI/Verifier: Fix argument bitrot in DILocalVariable	2015-07-24 23:59:25 +00:00
Hexagon	[Hexagon] Generate MUX from conditional transfers when dot-new not possible	2015-07-20 21:23:25 +00:00
Inputs
Mips
MIR	MIR Serialization: Serialize the unnamed basic block references.	2015-07-27 22:42:41 +00:00
MSP430
NVPTX	[BranchFolding] do not iterate the aliases of virtual registers	2015-07-22 04:16:52 +00:00
PowerPC	Fix PPCMaterializeInt to check the size of the integer based on the	2015-07-25 00:48:08 +00:00
SPARC
SystemZ
Thumb	[ARM] Make the frame lowering code ready for shrink-wrapping.	2015-07-22 16:34:37 +00:00
Thumb2	ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2	2015-07-21 00:18:59 +00:00
WebAssembly	WebAssembly: add a generic CPU	2015-07-27 23:25:54 +00:00
WinEH
X86	[X86][SSE] Use bitmasks instead of shuffles where possible.	2015-07-28 08:54:41 +00:00
XCore