Ben Langmuir a247e9d42b Add the remaining Intel SHA instructions ... Also assembly/disassembly tests, and for sha256rnds2, aliases with an explicit xmm0 dependency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190754 91177308-0d34-0410-b5e6-96231b3b80d8		2013-09-14 15:03:21 +00:00
..
AArch64	AArch64: use RegisterOperand for NEON registers.	2013-09-13 07:26:52 +00:00
ARM	Fix tests for hasFPARMv8 name change (r190692)	2013-09-13 14:37:52 +00:00
Mips	Fixed bug when generating Load Upper Immediate microMIPS instruction.	2013-09-14 07:35:41 +00:00
SystemZ	[SystemZ] Add TM and TMY	2013-09-10 10:20:32 +00:00
X86	Add the remaining Intel SHA instructions	2013-09-14 15:03:21 +00:00
XCore	[tests] Cleanup initialization of test suffixes.	2013-08-16 00:37:11 +00:00