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patterns. This allows emission of this code: t1: save -96, %o6, %o6 subcc %i0, %i1, %l0 move %icc, %i0, %i2 or %g0, %i2, %i0 restore %g0, %g0, %g0 retl nop instead of this: t1: save -96, %o6, %o6 subcc %i0, %i1, %l0 be .LBBt1_2 ! nop .LBBt1_1: ! or %g0, %i2, %i0 .LBBt1_2: ! restore %g0, %g0, %g0 retl nop for this: int %t1(int %a, int %b, int %c) { %tmp.2 = seteq int %a, %b %tmp3 = select bool %tmp.2, int %a, int %c ret int %tmp3 } git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25809 91177308-0d34-0410-b5e6-96231b3b80d8 |
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.. | ||
.cvsignore | ||
DelaySlotFiller.cpp | ||
FPMover.cpp | ||
Makefile | ||
README.txt | ||
SparcV8.h | ||
SparcV8.td | ||
SparcV8AsmPrinter.cpp | ||
SparcV8InstrFormats.td | ||
SparcV8InstrInfo.cpp | ||
SparcV8InstrInfo.h | ||
SparcV8InstrInfo.td | ||
SparcV8ISelDAGToDAG.cpp | ||
SparcV8RegisterInfo.cpp | ||
SparcV8RegisterInfo.h | ||
SparcV8RegisterInfo.td | ||
SparcV8Subtarget.cpp | ||
SparcV8Subtarget.h | ||
SparcV8TargetMachine.cpp | ||
SparcV8TargetMachine.h |
To-do ----- * Keep the address of the constant pool in a register instead of forming its address all of the time. * We can fold small constant offsets into the %hi/%lo references to constant pool addresses as well. * When in V9 mode, register allocate %icc[0-3].