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a1719c9130
Add ISel::visitShiftInst() to instruction select shift instructions. Add a comment in visitAdd about how to do 64 bit adds. X86InstrInfo.def: Add register-to-register move opcodes and shift opcodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4477 91177308-0d34-0410-b5e6-96231b3b80d8
74 lines
3.8 KiB
C++
74 lines
3.8 KiB
C++
//===-- X86InstructionInfo.def - X86 Instruction Information ----*- C++ -*-===//
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//
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// This file describes all of the instructions that the X86 backend uses. It
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// relys on an external 'I' macro being defined that takes the arguments
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// specified below, and is used to make all of the information relevant to an
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// instruction be in one place.
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//
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// Note that X86 Instructions always have the destination register listed as
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// operand 0, unless it does not produce a value (in which case the TSFlags will
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// include X86II::Void).
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//
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//===----------------------------------------------------------------------===//
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// NOTE: No include guards desired
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#ifndef I
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#errror "Must define I macro before including X86/X86InstructionInfo.def!"
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#endif
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// Arguments to be passed into the I macro
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// #1: Enum name - This ends up being the opcode symbol in the X86 namespace
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// #2: Opcode name, as used by the gnu assembler
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// #3: Instruction Flags - This should be a field or'd together that contains
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// constants from the MachineInstrInfo.h file.
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// #4: Target Specific Flags - Another bitfield containing X86 specific flags
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// that we are interested in for each instruction. These should be flags
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// defined in X86InstrInfo.h in the X86II namespace.
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//
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// The first instruction must always be the PHI instruction: (FIXME, not yet)
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I(PHI , "phi", 0, 0)
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// The second instruction must always be the noop instruction: (FIXME, not yet)
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I(NOOP , "nop", 0, X86II::Void) // nop 90
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// Miscellaneous instructions
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I(RET , "ret", M_RET_FLAG, X86II::Void) // ret CB
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// Move instructions
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I(MOVrr8 , "movb", 0, 0) // R8 = R8 88/r
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I(MOVrr16 , "movw", 0, 0) // R16 = R16 89/r
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I(MOVrr32 , "movl", 0, 0) // R32 = R32 89/r
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I(MOVir8 , "movb", 0, 0) // R8 = imm8 B0+ rb
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I(MOVir16 , "movw", 0, 0) // R16 = imm16 B8+ rw
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I(MOVir32 , "movl", 0, 0) // R32 = imm32 B8+ rd
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// Arithmetic instructions
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I(ADDrr8 , "addb", 0, 0) // R8 += R8 00/r
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I(ADDrr16 , "addw", 0, 0) // R16 += R16 01/r
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I(ADDrr32 , "addl", 0, 0) // R32 += R32 02/r
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// Shift instructions
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I(SHLrr8 , "shlb", 0, 0) // R8 <<= cl D2/4
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I(SHLir8 , "shlb", 0, 0) // R8 <<= imm8 C0/4 ib
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I(SHLrr16 , "shlw", 0, 0) // R16 <<= cl D3/4
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I(SHLir16 , "shlw", 0, 0) // R16 <<= imm8 C1/4 ib
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I(SHLrr32 , "shll", 0, 0) // R32 <<= cl D3/4
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I(SHLir32 , "shll", 0, 0) // R32 <<= imm8 C1/4 ib
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I(SHRrr8 , "shrb", 0, 0) // R8 >>>= cl D2/5
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I(SHRir8 , "shrb", 0, 0) // R8 >>>= imm8 C0/5 ib
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I(SHRrr16 , "shrw", 0, 0) // R16 >>>= cl D3/5
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I(SHRir16 , "shrw", 0, 0) // R16 >>>= imm8 C1/5 ib
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I(SHRrr32 , "shrl", 0, 0) // R32 >>>= cl D3/5
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I(SHRir32 , "shrl", 0, 0) // R32 >>>= imm8 C1/5 ib
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I(SARrr8 , "sarb", 0, 0) // R8 >>= cl D2/7
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I(SARir8 , "sarb", 0, 0) // R8 >>= imm8 C0/7 ib
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I(SARrr16 , "sarw", 0, 0) // R16 >>= cl D3/7
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I(SARir16 , "sarw", 0, 0) // R16 >>= imm8 C1/7 ib
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I(SARrr32 , "sarl", 0, 0) // R32 >>= cl D3/7
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I(SARir32 , "sarl", 0, 0) // R32 >>= imm8 C1/7 ib
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// At this point, I is dead, so undefine the macro
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#undef I
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