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InstSelectSimple.cpp: Include llvm/iOther.h for ShiftInst.
Add ISel::visitShiftInst() to instruction select shift instructions. Add a comment in visitAdd about how to do 64 bit adds. X86InstrInfo.def: Add register-to-register move opcodes and shift opcodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4477 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Brian Gaeke
parent
9b87c5c53c
commit
a1719c9130
@ -8,6 +8,7 @@
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#include "X86InstrInfo.h"
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#include "llvm/Function.h"
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#include "llvm/iTerminators.h"
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#include "llvm/iOther.h"
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#include "llvm/Type.h"
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#include "llvm/Constants.h"
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#include "llvm/Pass.h"
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@ -55,6 +56,7 @@ namespace {
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//
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void visitReturnInst(ReturnInst &RI);
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void visitAdd(BinaryOperator &B);
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void visitShiftInst(ShiftInst &I);
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void visitInstruction(Instruction &I) {
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std::cerr << "Cannot instruction select: " << I;
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@ -141,6 +143,186 @@ void ISel::visitReturnInst(ReturnInst &I) {
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BuildMI(BB, X86::RET, 0);
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}
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/// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
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/// for constant immediate shift values, and for constant immediate
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/// shift values equal to 1. Even the general case is sort of special,
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/// because the shift amount has to be in CL, not just any old register.
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///
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void
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ISel::visitShiftInst (ShiftInst & I)
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{
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unsigned Op0r = getReg (I.getOperand (0));
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unsigned DestReg = getReg (I);
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unsigned operandSize = I.getOperand (0)->getType ()->getPrimitiveSize ();
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bool isRightShift = (I.getOpcode () == Instruction::Shr);
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bool isOperandUnsigned = I.getType ()->isUnsigned ();
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bool isConstantShiftAmount = (isa <ConstantUInt> (I.getOperand (1)));
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if (ConstantUInt *CUI = dyn_cast <ConstantUInt> (I.getOperand (1)))
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{
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// The shift amount is constant. Get its value.
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uint64_t shAmt = CUI->getValue ();
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// Emit: <insn> reg, shamt (shift-by-immediate opcode "ir" form.)
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if (isRightShift)
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{
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if (isOperandUnsigned)
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{
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// This is a shift right logical (SHR).
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switch (operandSize)
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{
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case 1:
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BuildMI (BB, X86::SHRir8, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 2:
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BuildMI (BB, X86::SHRir16, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 4:
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BuildMI (BB, X86::SHRir32, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 8:
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default:
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visitInstruction (I);
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break;
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}
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}
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else
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{
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// This is a shift right arithmetic (SAR).
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switch (operandSize)
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{
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case 1:
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BuildMI (BB, X86::SARir8, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 2:
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BuildMI (BB, X86::SARir16, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 4:
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BuildMI (BB, X86::SARir32, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 8:
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default:
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visitInstruction (I);
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break;
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}
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}
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}
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else
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{
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// This is a left shift (SHL).
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switch (operandSize)
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{
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case 1:
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BuildMI (BB, X86::SHLir8, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 2:
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BuildMI (BB, X86::SHLir16, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 4:
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BuildMI (BB, X86::SHLir32, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 8:
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default:
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visitInstruction (I);
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break;
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}
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}
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}
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else
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{
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// The shift amount is non-constant.
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//
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// In fact, you can only shift with a variable shift amount if
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// that amount is already in the CL register, so we have to put it
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// there first.
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//
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// Get it from the register it's in.
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unsigned Op1r = getReg (I.getOperand (1));
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// Emit: move cl, shiftAmount (put the shift amount in CL.)
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BuildMI (BB, X86::MOVrr8, 2, X86::CL).addReg (Op1r);
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// Emit: <insn> reg, cl (shift-by-CL opcode; "rr" form.)
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if (isRightShift)
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{
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if (isOperandUnsigned)
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{
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// This is a shift right logical (SHR).
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switch (operandSize)
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{
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case 1:
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BuildMI (BB, X86::SHRrr8, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 2:
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BuildMI (BB, X86::SHRrr16, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 4:
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BuildMI (BB, X86::SHRrr32, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 8:
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default:
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visitInstruction (I);
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break;
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}
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}
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else
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{
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// This is a shift right arithmetic (SAR).
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switch (operandSize)
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{
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case 1:
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BuildMI (BB, X86::SARrr8, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 2:
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BuildMI (BB, X86::SARrr16, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 4:
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BuildMI (BB, X86::SARrr32, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 8:
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default:
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visitInstruction (I);
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break;
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}
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}
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}
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else
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{
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// This is a left shift (SHL).
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switch (operandSize)
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{
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case 1:
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BuildMI (BB, X86::SHLrr8, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 2:
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BuildMI (BB, X86::SHLrr16, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 4:
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BuildMI (BB, X86::SHLrr32, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 8:
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default:
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visitInstruction (I);
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break;
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}
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}
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}
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}
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/// 'add' instruction - Simply turn this into an x86 reg,reg add instruction.
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void ISel::visitAdd(BinaryOperator &B) {
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@ -157,13 +339,18 @@ void ISel::visitAdd(BinaryOperator &B) {
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case 4: // UInt, Int
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BuildMI(BB, X86::ADDrr32, 2, DestReg).addReg(Op0r).addReg(Op1r);
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break;
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case 8: // ULong, Long
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// Here we have a pair of operands each occupying a pair of registers.
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// We need to do an ADDrr32 of the least-significant pair immediately
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// followed by an ADCrr32 (Add with Carry) of the most-significant pair.
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// I don't know how we are representing these multi-register arguments.
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default:
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visitInstruction(B); // abort
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}
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}
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/// createSimpleX86InstructionSelector - This pass converts an LLVM function
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/// into a machine code representation is a very simple peep-hole fashion. The
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/// generated code sucks but the implementation is nice and simple.
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@ -8,6 +8,7 @@
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#include "X86InstrInfo.h"
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#include "llvm/Function.h"
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#include "llvm/iTerminators.h"
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#include "llvm/iOther.h"
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#include "llvm/Type.h"
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#include "llvm/Constants.h"
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#include "llvm/Pass.h"
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@ -55,6 +56,7 @@ namespace {
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//
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void visitReturnInst(ReturnInst &RI);
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void visitAdd(BinaryOperator &B);
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void visitShiftInst(ShiftInst &I);
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void visitInstruction(Instruction &I) {
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std::cerr << "Cannot instruction select: " << I;
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@ -141,6 +143,186 @@ void ISel::visitReturnInst(ReturnInst &I) {
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BuildMI(BB, X86::RET, 0);
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}
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/// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
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/// for constant immediate shift values, and for constant immediate
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/// shift values equal to 1. Even the general case is sort of special,
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/// because the shift amount has to be in CL, not just any old register.
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///
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void
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ISel::visitShiftInst (ShiftInst & I)
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{
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unsigned Op0r = getReg (I.getOperand (0));
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unsigned DestReg = getReg (I);
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unsigned operandSize = I.getOperand (0)->getType ()->getPrimitiveSize ();
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bool isRightShift = (I.getOpcode () == Instruction::Shr);
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bool isOperandUnsigned = I.getType ()->isUnsigned ();
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bool isConstantShiftAmount = (isa <ConstantUInt> (I.getOperand (1)));
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if (ConstantUInt *CUI = dyn_cast <ConstantUInt> (I.getOperand (1)))
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{
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// The shift amount is constant. Get its value.
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uint64_t shAmt = CUI->getValue ();
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// Emit: <insn> reg, shamt (shift-by-immediate opcode "ir" form.)
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if (isRightShift)
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{
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if (isOperandUnsigned)
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{
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// This is a shift right logical (SHR).
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switch (operandSize)
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{
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case 1:
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BuildMI (BB, X86::SHRir8, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 2:
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BuildMI (BB, X86::SHRir16, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 4:
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BuildMI (BB, X86::SHRir32, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 8:
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default:
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visitInstruction (I);
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break;
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}
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}
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else
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{
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// This is a shift right arithmetic (SAR).
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switch (operandSize)
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{
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case 1:
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BuildMI (BB, X86::SARir8, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 2:
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BuildMI (BB, X86::SARir16, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 4:
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BuildMI (BB, X86::SARir32, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 8:
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default:
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visitInstruction (I);
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break;
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}
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}
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}
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else
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{
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// This is a left shift (SHL).
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switch (operandSize)
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{
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case 1:
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BuildMI (BB, X86::SHLir8, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 2:
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BuildMI (BB, X86::SHLir16, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 4:
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BuildMI (BB, X86::SHLir32, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 8:
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default:
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visitInstruction (I);
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break;
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}
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}
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}
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else
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{
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// The shift amount is non-constant.
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//
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// In fact, you can only shift with a variable shift amount if
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// that amount is already in the CL register, so we have to put it
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// there first.
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//
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// Get it from the register it's in.
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unsigned Op1r = getReg (I.getOperand (1));
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// Emit: move cl, shiftAmount (put the shift amount in CL.)
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BuildMI (BB, X86::MOVrr8, 2, X86::CL).addReg (Op1r);
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// Emit: <insn> reg, cl (shift-by-CL opcode; "rr" form.)
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if (isRightShift)
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{
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if (isOperandUnsigned)
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{
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// This is a shift right logical (SHR).
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switch (operandSize)
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{
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case 1:
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BuildMI (BB, X86::SHRrr8, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 2:
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BuildMI (BB, X86::SHRrr16, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 4:
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BuildMI (BB, X86::SHRrr32, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 8:
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default:
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visitInstruction (I);
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break;
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}
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}
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else
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{
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// This is a shift right arithmetic (SAR).
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switch (operandSize)
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{
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case 1:
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BuildMI (BB, X86::SARrr8, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 2:
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BuildMI (BB, X86::SARrr16, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 4:
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BuildMI (BB, X86::SARrr32, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 8:
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default:
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visitInstruction (I);
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break;
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}
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}
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}
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else
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{
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// This is a left shift (SHL).
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switch (operandSize)
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{
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case 1:
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BuildMI (BB, X86::SHLrr8, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 2:
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BuildMI (BB, X86::SHLrr16, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 4:
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BuildMI (BB, X86::SHLrr32, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 8:
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default:
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visitInstruction (I);
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break;
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}
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}
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}
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}
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/// 'add' instruction - Simply turn this into an x86 reg,reg add instruction.
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void ISel::visitAdd(BinaryOperator &B) {
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@ -157,13 +339,18 @@ void ISel::visitAdd(BinaryOperator &B) {
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case 4: // UInt, Int
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BuildMI(BB, X86::ADDrr32, 2, DestReg).addReg(Op0r).addReg(Op1r);
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break;
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case 8: // ULong, Long
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// Here we have a pair of operands each occupying a pair of registers.
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// We need to do an ADDrr32 of the least-significant pair immediately
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// followed by an ADCrr32 (Add with Carry) of the most-significant pair.
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// I don't know how we are representing these multi-register arguments.
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default:
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visitInstruction(B); // abort
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}
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}
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/// createSimpleX86InstructionSelector - This pass converts an LLVM function
|
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/// into a machine code representation is a very simple peep-hole fashion. The
|
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/// generated code sucks but the implementation is nice and simple.
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@ -37,15 +37,37 @@ I(NOOP , "nop", 0, X86II::Void) // nop 90
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I(RET , "ret", M_RET_FLAG, X86II::Void) // ret CB
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// Move instructions
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I(MOVir8 , "movb", 0, 0) // R = imm8 B0+ rb
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I(MOVir16 , "movw", 0, 0) // R = imm16 B8+ rw
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I(MOVir32 , "movl", 0, 0) // R = imm32 B8+ rd
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I(MOVrr8 , "movb", 0, 0) // R8 = R8 88/r
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I(MOVrr16 , "movw", 0, 0) // R16 = R16 89/r
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I(MOVrr32 , "movl", 0, 0) // R32 = R32 89/r
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I(MOVir8 , "movb", 0, 0) // R8 = imm8 B0+ rb
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I(MOVir16 , "movw", 0, 0) // R16 = imm16 B8+ rw
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I(MOVir32 , "movl", 0, 0) // R32 = imm32 B8+ rd
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// Arithmetic instructions
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I(ADDrr8 , "addb", 0, 0) // R8 += R8 00/r
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I(ADDrr16 , "addw", 0, 0) // R16 += R16 01/r
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I(ADDrr32 , "addl", 0, 0) // R32 += R32 02/r
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// Shift instructions
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I(SHLrr8 , "shlb", 0, 0) // R8 <<= cl D2/4
|
||||
I(SHLir8 , "shlb", 0, 0) // R8 <<= imm8 C0/4 ib
|
||||
I(SHLrr16 , "shlw", 0, 0) // R16 <<= cl D3/4
|
||||
I(SHLir16 , "shlw", 0, 0) // R16 <<= imm8 C1/4 ib
|
||||
I(SHLrr32 , "shll", 0, 0) // R32 <<= cl D3/4
|
||||
I(SHLir32 , "shll", 0, 0) // R32 <<= imm8 C1/4 ib
|
||||
I(SHRrr8 , "shrb", 0, 0) // R8 >>>= cl D2/5
|
||||
I(SHRir8 , "shrb", 0, 0) // R8 >>>= imm8 C0/5 ib
|
||||
I(SHRrr16 , "shrw", 0, 0) // R16 >>>= cl D3/5
|
||||
I(SHRir16 , "shrw", 0, 0) // R16 >>>= imm8 C1/5 ib
|
||||
I(SHRrr32 , "shrl", 0, 0) // R32 >>>= cl D3/5
|
||||
I(SHRir32 , "shrl", 0, 0) // R32 >>>= imm8 C1/5 ib
|
||||
I(SARrr8 , "sarb", 0, 0) // R8 >>= cl D2/7
|
||||
I(SARir8 , "sarb", 0, 0) // R8 >>= imm8 C0/7 ib
|
||||
I(SARrr16 , "sarw", 0, 0) // R16 >>= cl D3/7
|
||||
I(SARir16 , "sarw", 0, 0) // R16 >>= imm8 C1/7 ib
|
||||
I(SARrr32 , "sarl", 0, 0) // R32 >>= cl D3/7
|
||||
I(SARir32 , "sarl", 0, 0) // R32 >>= imm8 C1/7 ib
|
||||
|
||||
// At this point, I is dead, so undefine the macro
|
||||
#undef I
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user