mirror of
https://github.com/c64scene-ar/llvm-6502.git
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1c3ef90cab
The vld1-lane, vld1-dup and vst1-lane instructions do not yet support using post-increment versions, but all the rest of the NEON load/store instructions should be handled now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125014 91177308-0d34-0410-b5e6-96231b3b80d8
159 lines
6.4 KiB
LLVM
159 lines
6.4 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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%struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> }
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%struct.__neon_int16x4x3_t = type { <4 x i16>, <4 x i16>, <4 x i16> }
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%struct.__neon_int32x2x3_t = type { <2 x i32>, <2 x i32>, <2 x i32> }
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%struct.__neon_float32x2x3_t = type { <2 x float>, <2 x float>, <2 x float> }
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%struct.__neon_int64x1x3_t = type { <1 x i64>, <1 x i64>, <1 x i64> }
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%struct.__neon_int8x16x3_t = type { <16 x i8>, <16 x i8>, <16 x i8> }
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%struct.__neon_int16x8x3_t = type { <8 x i16>, <8 x i16>, <8 x i16> }
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%struct.__neon_int32x4x3_t = type { <4 x i32>, <4 x i32>, <4 x i32> }
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%struct.__neon_float32x4x3_t = type { <4 x float>, <4 x float>, <4 x float> }
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define <8 x i8> @vld3i8(i8* %A) nounwind {
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;CHECK: vld3i8:
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;Check the alignment value. Max for this instruction is 64 bits:
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;CHECK: vld3.8 {d16, d17, d18}, [r0, :64]
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%tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 32)
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%tmp2 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 2
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%tmp4 = add <8 x i8> %tmp2, %tmp3
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ret <8 x i8> %tmp4
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}
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define <4 x i16> @vld3i16(i16* %A) nounwind {
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;CHECK: vld3i16:
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;CHECK: vld3.16
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i8* %tmp0, i32 1)
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%tmp2 = extractvalue %struct.__neon_int16x4x3_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int16x4x3_t %tmp1, 2
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%tmp4 = add <4 x i16> %tmp2, %tmp3
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ret <4 x i16> %tmp4
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}
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;Check for a post-increment updating load with register increment.
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define <4 x i16> @vld3i16_update(i16** %ptr, i32 %inc) nounwind {
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;CHECK: vld3i16_update:
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;CHECK: vld3.16 {d16, d17, d18}, [r2], r1
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%A = load i16** %ptr
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i8* %tmp0, i32 1)
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%tmp2 = extractvalue %struct.__neon_int16x4x3_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int16x4x3_t %tmp1, 2
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%tmp4 = add <4 x i16> %tmp2, %tmp3
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%tmp5 = getelementptr i16* %A, i32 %inc
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store i16* %tmp5, i16** %ptr
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ret <4 x i16> %tmp4
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}
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define <2 x i32> @vld3i32(i32* %A) nounwind {
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;CHECK: vld3i32:
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;CHECK: vld3.32
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i8* %tmp0, i32 1)
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%tmp2 = extractvalue %struct.__neon_int32x2x3_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int32x2x3_t %tmp1, 2
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%tmp4 = add <2 x i32> %tmp2, %tmp3
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ret <2 x i32> %tmp4
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}
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define <2 x float> @vld3f(float* %A) nounwind {
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;CHECK: vld3f:
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;CHECK: vld3.32
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3.v2f32(i8* %tmp0, i32 1)
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%tmp2 = extractvalue %struct.__neon_float32x2x3_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_float32x2x3_t %tmp1, 2
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%tmp4 = fadd <2 x float> %tmp2, %tmp3
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ret <2 x float> %tmp4
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}
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define <1 x i64> @vld3i64(i64* %A) nounwind {
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;CHECK: vld3i64:
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;Check the alignment value. Max for this instruction is 64 bits:
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;CHECK: vld1.64 {d16, d17, d18}, [r0, :64]
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%tmp0 = bitcast i64* %A to i8*
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%tmp1 = call %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64(i8* %tmp0, i32 16)
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%tmp2 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 2
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%tmp4 = add <1 x i64> %tmp2, %tmp3
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ret <1 x i64> %tmp4
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}
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define <16 x i8> @vld3Qi8(i8* %A) nounwind {
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;CHECK: vld3Qi8:
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;Check the alignment value. Max for this instruction is 64 bits:
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;CHECK: vld3.8 {d16, d18, d20}, [r0, :64]!
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;CHECK: vld3.8 {d17, d19, d21}, [r0, :64]
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%tmp1 = call %struct.__neon_int8x16x3_t @llvm.arm.neon.vld3.v16i8(i8* %A, i32 32)
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%tmp2 = extractvalue %struct.__neon_int8x16x3_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int8x16x3_t %tmp1, 2
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%tmp4 = add <16 x i8> %tmp2, %tmp3
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ret <16 x i8> %tmp4
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}
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define <8 x i16> @vld3Qi16(i16* %A) nounwind {
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;CHECK: vld3Qi16:
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;CHECK: vld3.16
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;CHECK: vld3.16
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3.v8i16(i8* %tmp0, i32 1)
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%tmp2 = extractvalue %struct.__neon_int16x8x3_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int16x8x3_t %tmp1, 2
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%tmp4 = add <8 x i16> %tmp2, %tmp3
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ret <8 x i16> %tmp4
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}
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define <4 x i32> @vld3Qi32(i32* %A) nounwind {
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;CHECK: vld3Qi32:
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;CHECK: vld3.32
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;CHECK: vld3.32
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32(i8* %tmp0, i32 1)
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%tmp2 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 2
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%tmp4 = add <4 x i32> %tmp2, %tmp3
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ret <4 x i32> %tmp4
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}
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;Check for a post-increment updating load.
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define <4 x i32> @vld3Qi32_update(i32** %ptr) nounwind {
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;CHECK: vld3Qi32_update:
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;CHECK: vld3.32 {d16, d18, d20}, [r1]!
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;CHECK: vld3.32 {d17, d19, d21}, [r1]!
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%A = load i32** %ptr
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32(i8* %tmp0, i32 1)
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%tmp2 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 2
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%tmp4 = add <4 x i32> %tmp2, %tmp3
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%tmp5 = getelementptr i32* %A, i32 12
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store i32* %tmp5, i32** %ptr
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ret <4 x i32> %tmp4
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}
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define <4 x float> @vld3Qf(float* %A) nounwind {
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;CHECK: vld3Qf:
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;CHECK: vld3.32
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;CHECK: vld3.32
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = call %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3.v4f32(i8* %tmp0, i32 1)
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%tmp2 = extractvalue %struct.__neon_float32x4x3_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_float32x4x3_t %tmp1, 2
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%tmp4 = fadd <4 x float> %tmp2, %tmp3
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ret <4 x float> %tmp4
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}
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declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8*, i32) nounwind readonly
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declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i8*, i32) nounwind readonly
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declare %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i8*, i32) nounwind readonly
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declare %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3.v2f32(i8*, i32) nounwind readonly
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declare %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64(i8*, i32) nounwind readonly
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declare %struct.__neon_int8x16x3_t @llvm.arm.neon.vld3.v16i8(i8*, i32) nounwind readonly
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declare %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3.v8i16(i8*, i32) nounwind readonly
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declare %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32(i8*, i32) nounwind readonly
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declare %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3.v4f32(i8*, i32) nounwind readonly
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