Bruno Cardoso Lopes 79abd1c27c Since ARM's prefetch implementation predicted the presence of a instruction ...

cache prefetch and now that the info from "prefetch" to "ARMPreload" is present,
only add a testcase for PLI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132978 91177308-0d34-0410-b5e6-96231b3b80d8

2011-06-14 05:11:46 +00:00

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Alpha

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ARM

Since ARM's prefetch implementation predicted the presence of a instruction

2011-06-14 05:11:46 +00:00

Blackfin

Don't completely eliminate identity copies that also modify super register liveness.

2011-03-31 17:55:25 +00:00

CBackend

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CellSPU

don't test for codegen of 'store undef'

2011-04-09 02:31:26 +00:00

CPP

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Generic

Move the legalizer tests to the X86 directory because the test uses the x86

2011-06-07 05:23:58 +00:00

MBlaze

Add scheduling information for the MBlaze backend.

2011-04-11 22:31:52 +00:00

Mips

Speculatively revert 132758 and 132768 to try to fix the Windows buildbots.

2011-06-09 16:03:19 +00:00

MSP430

Fix register-dependent test in MSP430.

2011-05-04 01:01:39 +00:00

PowerPC

Fix wrong usages of CTR/MCTR where CTR8/MCTR8 was meant.

2011-06-03 15:47:49 +00:00

PTX

PTX: add flag to disable mad/fma selection

2011-05-18 15:42:23 +00:00

SPARC

Fix more register and coalescing dependencies.

2011-05-04 19:02:11 +00:00

SystemZ

Fix SystemZ tests

2011-03-31 23:02:12 +00:00

Thumb

Move this test to CodeGen/Thumb. rdar://problem/9416774

2011-05-11 19:41:28 +00:00

Thumb2

AnalyzeBranch doesn't change which successors a bb has, just the order

2011-06-12 03:20:32 +00:00

X86

Add one more argument to the prefetch intrinsic to indicate whether it's a data

2011-06-14 04:58:37 +00:00

XCore

Add XCore intrinsic for crc8.

2011-05-31 16:24:49 +00:00